AXIOMTEK SBC8166, Руководство пользователя

Страница: 49 / 90

SBC8166 Socket370 Full-size CPU Card Series User’s Manual
Award BIOS Setup
(!
/ 6!!
" M
SDRAM RAS-to-CAS Delay : 3 Auto Detect DIMM/PCI Clk : Enabled
SDRAM RAS Precharge Time : 3 Spread Spectrum : Disabled
SDRAM CAS latency Time : 3 CPU Host Clock : Default
SDRAM Precharge Control : Disabled CPU Warning Temperature : Disabled
DRAM Data Integrity Mode : Non-ECC Current System Temp. : 49
o
C/120
o
F
System BIOS Cacheable : Disabled Current CPU Temperature : 49
o
C/120
o
F
Video BIOS Cacheable : Disabled Current CPU FAN1 Speed : 0RPM
Video RAM Cacheable : Disabled Current CPU FAN2 Speed : 0RPM
8 Bit I/O Recovery Time : 1 Vcore(V): 1.63V VTT(V) : 1.50V
16 Bit I/O Recovery Time : 1 3.3V: 3.37V +5V : 5.05V
Memory Hole At 15M-16M : Disabled +12V: 12.34V -12V : -11.78V
Passive Release : Enabled -5V: -5.16V
Delayed Transaction : Disabled
ESC : Quit
Ç È Æ Å
: Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift)F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
z SDRAM RAS-to-CAS Delay
During DRAM refresh, both rows and columns are addressed
separately. This field allows you to determine the timing of transition
from Row Address Strobe (RAS) to Column Address Strobe (CAS). The
default setting is
3 .
z SDRAM RAS Precharge Time
The precharge time is the number of cycles for the RAS to accumulate
its charge before DRAM refreshes. If time is insufficient, refresh may
be incomplete and the DRAM may fail to retain data. The default
setting is 3 .
z SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer. The default setting
is 3 .