AXIOMTEK SBC8166, Руководство пользователя

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SBC8166 Socket370 Full-size CPU Card Series User’s Manual
Award BIOS Setup
(6
z
DRAM Data Integrity Mode
This option sets the data integrity mode of the DRAM installed in the
system. The default setting is
Non-ECC .
z
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH is cached, provided that the cache controller is
disabled.
z Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH
is cached, provided that the cache controller is disabled.
z
Video RAM Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any
program writes to this memory area, a memory access error may result.
z 8 Bit I/O Recovery Time
This option specifies the length of the delay (in sysclks) inserted
between consecutive 8-bit I/O operations. The settings are 1, 2, 3, 4, 5,
6, 7, or 8. The default setting is
3
.
z 16 Bit I/O Recovery Time
This option specifies the length of the delay (in sysclks) inserted
between consecutive 16-bit I/O operations. The settings are 1, 2, 3, 4,
5, 6, 7, or 8. The default setting is
2
.
z Memory Hole at 15MB - 16MB
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to 16MB
memory address space to ISA expansion cards. This makes memory
from 15MB and up unavailable to the system. Expansion cards can
only access memory up to 16MB. By default, this field is set to
Disabled
.
z Passive Release
When enabled, CPU to PCI bus accesses are allowed during passive
release. Otherwise, the arbiter only accepts another PCI master
access to local DRAM.
z Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select
Enabled
to support compliance with
PCI specification version 2.1. The default setting is Disabled .