
Figure B
The next figure illustrates the relationship between the signal when an external TTL-
level trigger is used:
Figure C
As before, if the delay is negative, the order of the SYNC and PULSE outputs is
reversed.
The delay and frequency (when in the internal mode) of the PULSE output can be
varied with front panel controls or via the GPIB or RS-232 computer interfaces.
22
SYNC OUT
(generated by the
internal oscillator)
100 ns, FIXED
Mainframe OUT
DELAY < 0
3V, FIXED
PW 1
PW 2
AMP1 (+),
VARIABLE
AMP2 (-),
VARIABLE
> 50 ns
TTL LEVELS
(0V and 3V-5V)
TRIG
(external input)
PROPAGATION DELAY (FIXED)
SYNC OUT
(generated by the
internal oscillator)
100 ns, FIXED
Mainframe OUT
PW 1
DELAY > 0
AMP1 (+),
VARIABLE
3V, FIXED
PW 2
AMP2 (-),
VARIABLE
Содержание AVR-EB4-B
Страница 45: ...The next photo shows a MELF device installed between the two pins 45 A MELF packaged Device Under Test DUT...
Страница 57: ...Then open the tan colored DUT socket by flipping forward the two black latches on the front edge of it 57...
Страница 69: ...PCB 158R5 LOW VOLTAGE POWER SUPPLY...
Страница 71: ...PCB 104G KEYPAD DISPLAY BOARD...
Страница 76: ...TEST JIG WIRING AVX TRR HPOST...
Страница 83: ...PERFORMANCE CHECK SHEET 83...