Version 1.0
Page 6
The following figure is a high level block diagram of the UltraZed-EG SOM and the peripherals attached to
the Zynq Ult MPSoC Processing Sub-System and Programmable Logic Sub-System.
MIO[0:12]
I2C
– MIO[24:25]
MIO[26:51]
MIO[52:63]
MIO[64:77]
GTR[0:3]
GTR_Ref_CLK[0:3]
HP I/O (90)
JTAG (4)
SYS MO N (4)
140
-P
in
C
o
n
n
e
c
to
r
(JX
1
)
S
ig
n
a
l(
90
),
G
N
D
(37
),
V
C
C
O
(6
),
V
IN
(3
),
J
T
A
G
(4
)
140
-P
in
C
o
n
n
e
c
to
r
(JX
2
)
S
ig
n
a
l(
90
),
G
N
D
(31
),
V
C
C
O
(6
),
V
IN
(3
),
S
Y
S
M
O
N
(4
),
P
M
B
u
s
(3
),
S
O
M
_
R
E
S
E
T
_
IN
,
CC
_
R
E
S
E
T
_
O
U
T
,
S
O
M
_
PG
_
O
U
T
Voltage Regulators
Input: 5
– 12V
Outputs:
0.6V, 0.85V, 1.0V, 1.2V,
1.25V,1.8V, 2.5V, 3.3V
100
-P
in
C
o
n
n
e
c
to
r
(JX
3
)
S
ig
n
a
l(
65
),
G
N
D
(19
),
G
T
R
A
V
C
C
(3
),
G
T
R
A
V
T
T
(2
),
S
e
n
se
(6
),
PS
_
V
B
A
T
T
,
CC
_
S
D
A
,
CC
_
S
C
L
,
CC
_
IN
T
,
V
C
C
O
_
P
S
IO
_
501
DDR4
(2GB, x32)
Dual QSPI
(64MB)
USB 2.0
ULPI PHY
Ethernet
RGMII PHY
MIO[13:22]
eMMC
(8GB, x8)
26
5
10
16
8
HP I/O (66)
HD I/O (24)
INT
– MIO[23]
PMBus (3)
2-Channel
I2C Switch/Mux
To PMBus
Regulators
SD1/SC1
SD0/SC0/INT0
SDA/SCL
Zynq Ult
ZU3EG-SFVA625
PS-Side
PL-Side
I2C 8-Bit
I/O Expander
I2C EEPROM
(2Kb)
3
Figure 2
– UltraZed-EG SOM Block Diagram
