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User’s Manual
ECM-CX700 Series User’s Manual 65
3.5.3.3 CPU & PCI Bus Control
Item Options Description
PCI Master 0 WS Write
Enabled
Disabled
To write PCI bus while zero wait state is executed.
PCI Delay Transaction
Enabled
Disabled
This feature is used to meet the latency of PCI cycles to
and from the ISA bus. The ISA bus is much, much slower
than the PCI bus. Thus, PCI cycles to and from the ISA
bus take a longer time to complete and this slows the PCI
bus down.
However, enabling
PCI Delayed Transaction enables
the chipset's embedded 32-bit posted write buffer to
support delayed transaction cycles. This means that
transactions to and from the ISA bus are buffered and the
PCI bus can be freed to perform other transactions while
the ISA transaction is underway.
This option should be
enabled for better performance
and to meet PCI 2.1 specifications. “Disabled” is set only
if the PCI cards cannot work properly or if an ISA card
that is not PCI 2.1 compliant is used.
VLink Mode Selection
By Auto
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4 The North Bridge interface to the South Bridge through a
high speed(up to 1GB/Sec)8x, 66MHz Data Transfer
interconnect bus caller “V-Link”. This item allows you to
select the V-Link mode from 0 to 4.
VLink 8X Support
Enabled
Disabled
The feature is to toggle the V-Link bus mode between the
original V-Link and the newer and faster 8X V-Link.
DRDY_Timing
Slowest
Default
Optimize
Allows to set the timing for each cycle that data is
transferred.
3.5.3.4 Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved it cannot be cached. The user information of peripherals that need to use this area
of system memory usually2 discussed their memory requirements.
The choices: Disabled, 15M-16M.