304
8331B–AVR–03/12
Atmel AVR XMEGA AU
23.9
Fractional Baud Rate Generation
Fractional baud rate generation is possible for asynchronous operation due to the relatively high
number of clock cycles for each frame. Each bit is sampled sixteen times, but only the three mid-
dle samples are of importance. The total number of samples for one frame is also relatively high.
Given a 1-start, 8-data, no-parity, and 1-stop-bit frame format, and assuming that normal speed
mode is used, the total number of samples for a frame is (1+8+1)×16 or 160. As stated earlier,
the UART can tolerate some variation in clock cycles for each sample. The critical factor is the
time from the falling edge of the start bit (i.e., the clock synchronization) until the last bit's (i.e.,
the first stop bit’s) value is recovered.
Standard baud rate generators have the unwanted property of having large frequency steps
between high baud rate settings. The worst case is found between the BSEL values 0x000 and
0x001. Going from a BSEL value of 0x000, which has a 10-bit frame of 160 clock cycles, to a
BSEL value of 0x001, with 320 clock cycles, gives a 50% change in frequency. Ideally, the step
size should be small even between the fastest baud rates. This is where the advantage of the
fractional baud rate generator emerges.
In principle, the fractional baud rate generator works by doing uneven counting and then distrib-
uting the error evenly over the entire frame. A typical count sequence for an ordinary baud rate
generator is:
2, 1, 0, 2, 1, 0, 2, 1, 0, 2, …
which has an even period time. A baud rate clock ticks each time the counter reaches zero, and
a sample of the signal received on RxD is taken for every 16th baud rate clock tick.
For the fractional baud rate generator, the count sequence can have an uneven period:
2, 1, 0, 2, 1-1, 0, 2, 1, 0, 2, 1-1, 0, ...
In this example, an extra cycle is added to every second baud clock. This gives a baud rate
clock tick jitter, but the average period has been increased by a fraction of 0.5 clock cycles.
shows an example of how BSEL and BSCALE can be used to achieve
baud rates in between what is possible by just changing BSEL.
The impact of fractional baud rate generation is that the step size between baud rate settings
has been reduced. Given a scale factor of -1, the worst-case step then becomes from 160 to 240
clock cycles per 10-bit frame, compared to the previous step of from 160 to 320. A higher nega-
tive scale factor gives even finer granularity. There is a limit,however, to how high the scale
factor can be. The value 2
|BSCALE|
must be at most half the minimum number of clock cycles of a
frame. For instance, for 10-bit frames, the minimum number of clock cycles is 160. This means
that the highest applicable scale factor is -6 (2
I-6I
= 64 < (160/2) = 80)
For higher BSEL settings, the scale factor can be increased.
shows BSEL and BSCALE settings when using the internal oscillators
to generate the most commonly used baud rates for asynchronous operation and how reducing
the BSCALE can be used to reduce the baud rate error even further.
