Atmel AVR XMEGA AU series, Руководство пользователя

Страница: 232 / 512

232
8331B–AVR–03/12
Atmel AVR XMEGA AU
After writing a byte in the PER register, the write (HW/SW) condition for setting OVFIF and the
overflow wake-up condition are disabled for the following two RTC32 clock cycles.
19.3.10 PER1 – Period register 1
19.3.11 PER2 – Period register 2
19.3.12 PER3 – Period register 3
19.3.13 COMP0 – Compare register 0
The COMP0, COMP1, COMP2, and COMP3 registers represents the 32-bit value, COMP.
COMP is constantly compared with the counter value (CNT). A compare match will set COMPIF
in the INTFLAGS register, and an interrupt is generated if it is enabled. COMPIF will be set on
next count after a match.
If the COMP value is higher than the PER value, no RTC compare match interrupt requests or
events will be generated.
After writing the high byte of the COMP register, the write condition for setting OVFIF and COM-
PIF, as well as the overflow and compare match wake-up condition, will be disabled for the
following two RTC32 clock cycles.
Bit 7 6 5 4 3 2 1 0
+0x08
PER[7:0] PER0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x09
PER[15:8] PER1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0A
PER[23:16] PER2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0B PER[31:24] PER3
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0