25
ATtiny22/22L
•
Bit 4 - SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode.
When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the section “Sleep Modes” on
page 25.
•
Bits 3, 2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny22/L, and always read as zero.
•
Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set.
The level and edges on the external INT0 pin that activate the interrupt are defined in Table 7. The value on the INT01 pin
is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low
level must be held until the completion of the currently executing instruction to generate an interrupt.
Note:
When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Other-
wise an interrupt can occur when the bits are changed.
Sleep Modes
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an
enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes
execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector.
Idle Mode
When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode stopping the CPU but allowing
Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external
triggered interrupts as well as internal ones like Timer Overflow interrupt and watchdog reset.
Power Down Mode
When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power Down Mode. In this mode, the external
oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset,
a watchdog reset (if enabled), or an external level interrupt on INT0 can wake up the MCU.
Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for
some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the
watchdog oscillator clock, and if the input has the required level during this time, the MCU will wake up. The period of the
watchdog oscillator is 1 us (nominal) at 5.0V and 25C. The frequency of the watchdog oscillator is voltage dependent as
shown in section “Typical characteristics” on page 44.
When waking up from Power Down Mode, there is a delay from the wake-up condition occurs until the wake-up becomes
effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is equal to the
clock reset period, as shown in Table 3 and Table 4.
If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g. a low level on is not held long
enough, the interrupt causing the wake-up will not be executed.
Table 7. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Reserved
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
