23
ATtiny22/22L
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
General Interrupt Mask Register - GIMSK
•
Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny22/L and always reads as zero.
•
Bit 6 - INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether
the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an
interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from program memory address $001. See also “External Interrupts.”
•
Bits 5..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny22/L and always read as zero.
General Interrupt Flag Register - GIFR
•
Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny22/L and always reads as zero.
•
Bit 6 - INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
•
Bits 5..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny22/L and always read as zero.
Timer/Counter Interrupt Mask Register - TIMSK
•
Bit 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny22/L and always read zero.
•
Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the
Overflow Flag (Timer/Counter0) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
•
Bit 0 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny22/L and always reads as zero.
Bit
7
6
5
4
3
2
1
0
$3B ($5B)
-
INT0
-
-
-
-
-
-
GIMSK
Read/Write
R
R/W
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$3A ($5A)
-
INTF0
-
-
-
-
-
-
GIFR
Read/Write
R
R/W
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$39 ($59)
-
-
-
-
-
-
TOIE0
-
TIMSK
Read/Write
R
R
R
R
R
R
R/W
R
Initial value
0
0
0
0
0
0
0
0
