24
ATtiny22/22L
Timer/Counter Interrupt FLAG Register - TIFR
•
Bits 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny22/L and always read zero.
•
Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical one to the flag. When the SREG
I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow inter-
rupt is executed.
•
Bit 0 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny22/L and always reads zero.
External Interrupt
The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is
configured as an output. This feature provides a way of generating a software interrupt. The external interrupt can be trig-
gered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register
- MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as
the pin is held low.
The external interrupt is set up as described in the specification for the MCU Control Register - MCUCR.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the
interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During these 4
clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the
I flag in SREG is set. The vector is a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt
occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock
cycles, the Program Counter (2 bytes) is popped back from the Stack, and the Stack Pointer is incremented by 2. When the
AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending
interrupt is served.
MCU Control Register - MCUCR
The MCU Control Register contains control bits for general MCU functions.
•
Bits 7, 6 - Res: Reserved Bits
These bits are reserved bits in the ATtiny22/L and always read as zero.
•
Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the
MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just
before the execution of the SLEEP instruction.
Bit
7
6
5
4
3
2
1
0
$38 ($58)
-
-
-
-
-
-
TOV0
-
TIFR
Read/Write
R
R
R
R
R
R
R/W
R
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$35 ($55)
-
-
SE
SM
-
-
ISC01
ISC00
MCUCR
Read/Write
R
R
R/W
R/W
R
R
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
