ATtiny15L
32
The Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1 MHz. This is the typical value at V
CC
=
5V. See characterization data for typical values at other V
CC
levels. By controlling the Watchdog Timer prescaler, the
Watchdog reset interval can be adjusted from 16 to 2048 ms as shown in Table 15. The WDR – Watchdog Reset – instruc-
tion resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the
reset period expires without another Watchdog reset, the ATtiny15L resets and executes from the reset vector. For timing
details on the Watchdog reset, refer to page 17.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is dis-
abled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 23.
Watchdog Timer
The Watchdog Timer Control Register – WDTCR
•
Bits 7..5 - Res: Reserved bits
These bits are reserved bits in the ATtiny15L and will always read as zero.
•
Bit 4 - WDTOE: Watch Dog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware
will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
•
Bit 3 - WDE: Watch Dog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function
is disabled. WDE can be cleared only when the WDTOE bit is set(one). To disable an enabled watchdog timer, the follow-
ing procedure must be followed:
1.
In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though
it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.
•
Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler bits 2, 1, and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The
different prescaling values and their corresponding time-out periods are shown in Table 15.
Bit
7
6
5
4
3
2
1
0
$21
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
1 MHz at Vcc = 5V
350 KHz at Vcc = 3V
WATCHDOG
PRESCALER
WATCHDOG
Oscillator
RESET
WDP0
WDP1
WDP2
WDE
MCU RESET
