ATtiny15L
11
The Status Register – SREG
The AVR status register – SREG – at I/O space location $3F is defined as:
•
Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is
then performed in the interrupt mask registers – GIMSK and TIMSK. If the global interrupt enable register is cleared (zero),
none of the interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
•
Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A
bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
•
Bit 5 - H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the Instruction Set Description for detailed
information.
•
Bit 4 - S: Sign Bit, S = N
⊕
V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-
tion Set Description for detailed information.
•
Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for
detailed information.
•
Bit 2 - N: Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set
Description for detailed information.
•
Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description
for detailed information.
•
Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed
information.
Reset and Interrupt Handling
The ATtiny15L provides 8 interrupt sources. These interrupts and the separate reset vector, each have a separate program
vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together
with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt
Request 0 etc.
Bit
7
6
5
4
3
2
1
0
$3F
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
