ATtiny15L
20
The Timer/Counter Interrupt Mask Register – TIMSK
•
Bit 7 - Res: Reserved bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
•
Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one)and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match, inter-
rupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match A in Timer/Counter1 occurs,
i.e. when the OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
•
Bit 5..3 - Res: Reserved bits
These bits are reserved bits in the ATtiny15L and always read as zero.
•
Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is
enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs, i.e. when the
TOV1 bit is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
•
Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $005) is executed if an overflow in Timer/Counter0 occurs, i.e. when the
TOV0 bit is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
•
Bit 0 - Res: Reserved bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
The Timer/Counter Interrupt Flag Register – TIFR
•
Bit 7 - Res: Reserved bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
•
Bit 6 - OCF1A: Output Compare Flag 1 A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A – Output
Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-
tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the
Timer/Counter1 compare match A interrupt is executed.
•
Bits 5..3 - Res: Reserved bits
These bits are reserved bits in the ATtiny15L and always read as zero.
•
Bit 2 - TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical one to the flag. When the SREG
I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow inter-
rupt is executed.
•
Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical one to the flag. When the SREG
I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow inter-
rupt is executed.
•
Bit 0 - Res: Reserved bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
Bit
7
6
5
4
3
2
1
0
$39
-
OCIE1A
-
-
-
TOIE1
TOIE0
-
TIMSK
Read/Write
R
R/W
R
R
R
R/W
R/W
R
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$38
-
OCF1A
-
-
-
TOV1
TOV0
-
TIFR
Read/Write
R
R/W
R
R
R
R/W
R/W
R
Initial value
0
0
0
0
0
0
0
0
