ATtiny15L
53
High-voltage Serial Programming Characteristics
Figure 32.
High-voltage Serial Programming Timing
Low-voltage Serial Downloading
Both the Program and Data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The
serial interface consists of pins SCK, MOSI (input) and MISO (output), see Figure 33. After RESET is set low, the Program-
ming Enable instruction needs to be executed first before program/erase instructions can be executed.
Figure 33.
Serial Programming and Verify
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first exe-
cute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
The Program and EEPROM memory arrays have separate address spaces:
$0000 to $01FF for Program memory and $000 to $03F for EEPROM memory.
The device is clocked from the internal clock at the uncalibrated minimum frequency (0.8 - 1.6 MHz). The minimum low and
high periods for the serial clock (SCK) input are defined as follows:
Low: > 2 MCU clock cycles
High: > 2 MCU clock cycles
Table 25.
High-voltage Serial Programming Characteristics
T
A
= 25
°
C ± 10%, V
CC
= 5.0V ± 10% (Unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
Units
t
SHSL
SCI (PB3) Pulse-width High
25
ns
t
SLSH
SCI (PB3) Pulse-width Low
25
ns
t
IVSH
SDI (PB0), SII (PB1) Valid to SCI (PB3) High (8´th edge)
50
ns
t
SHIX
SDI (PB0), SII (PB1) Hold after SCI (PB3) High (8´th edge)
50
ns
t
SHOV
SCI (PB3) High (9´th edge) to SDO (PB2) Valid
10
16
32
ns
SDI (PB0), SII (PB1)
SDO (PB2)
SCI (PB3)
t
IVSH
t
SHSL
t
SLSH
t
SHIX
t
SHOV
Internal CK
1 2 7 8 9 10 15 16
VALID
PB5 (RESET)
GND
VCC
PB2
PB1
PB0
SCK
MISO
MOSI
2.7 - 5.5V
ATtiny15/L
GND
