Atmel AT91FR40162S, Руководство пользователя

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6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
Figure 10-11. Early Read Wait State
10.8 Write Data Hold Time
During write cycles in both protocols, output data becomes valid after the falling edge of the
NWE signal and remains valid after the rising edge of NWE, as illustrated in
Figure 10-12 . The
external NWE waveform (on the NWE pin) is used to control the output data timing to guarantee
this operation.
It is therefore necessary to avoid excessive loading of the NWE pins, which could delay the write
signal too long and cause a contention with a subsequent read cycle in standard protocol.
Figure 10-12. Data Hold Time
In early read protocol the data can remain valid longer than in standard read protocol due to the
additional wait cycle which follows a write access.
ADDR
NCS
NWE
MCKI
Write Cycle Early Read Wait Read Cycle
NRD
ADDR
NWE
Data Output
MCK