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AT40K Series Configuration

1009B–FPGA–03/02

After a configuration clear cycle, the user logic of the FPGA is set to a benign state, see
Table 4.

There is no activity in either the user logic or the configuration logic and the device is in
a low power state.

Table 3.

Configuration Clear Cycle Times

Device

Array Size

Clear Cycle Time

Units

Min

Typ

Max

AT40K05

16 x 16

137

228

365

µs

AT40K10

24 x 24

197

328

525

µs

AT40K20

32 x 32

257

428

685

µs

AT40K30

40 x 40

317

528

845

µs

AT40K40

48 x 48

377

628

1005

µs

Table 4.

User Circuitry and Default States

User Circuitry

Default State

Core

Inputs tied off

Local drivers off

DFF set

Repeater

All drivers off

Passgates off

I/O

Output drivers off

CMOS threshold

Pull-up enabled

Pull-down disabled

Clocks

Tied High

Resets

Tied Low (active)

RAM

Disabled

Contents cleared

Содержание AT40K

Страница 1: ...power is first applied to the part The FPGA initiates a complete clearing of all internal configuration SRAM configuration clear cycle The second manual reset occurs when the RESET pin is driven Low...

Страница 2: ...e or 16 bit wide parallel data In Slave Parallel Up Mode the device receives either 8 bit or 16 bit wide parallel data and generates a 20 bit address up counter for use in addressing memories CCLK is...

Страница 3: ...Trigger Input 50K Pull up Schmitt Trigger Input 50K Pull up Schmitt Trigger Input 50K Pull up Schmitt Trigger Input 50K Pull up HDC Output Output Output Output Output Output User I O User I O LDC Out...

Страница 4: ...ain an open drain bi directional pin which signals if an error is encountered during the download of a configuration bit stream In addition during the Check Function the INIT pin drives Low for any co...

Страница 5: ...D15 pins will transition from the user programmed state to CMOS inputs with nominal 20K internal pull up resistors as the SRAM at those locations is cleared by the configuration clear cycle When in M...

Страница 6: ...ces causes the INIT pin to go Low During power on reset or manual reset CHECK is controlled by the configura tion SRAM The CHECK pin will transition from the user programmed state to a CMOS input with...

Страница 7: ...ation clear cycle Once INIT goes High the mode pins are sampled If Mode 0 is detected the part proceeds to the configuration download state CON is held Low by the FPGA HDC remains High LDC remains Low...

Страница 8: ...ce Array Size Clear Cycle Time Units Min Typ Max AT40K05 16 x 16 137 228 365 s AT40K10 24 x 24 197 328 525 s AT40K20 32 x 32 257 428 685 s AT40K30 40 x 40 317 528 845 s AT40K40 48 x 48 377 628 1005 s...

Страница 9: ...tegration a bit in the control register CR31 may be set which com mands all I O pins not part of the configuration interface to go tri stated This bit is set at the start of configuration so the very...

Страница 10: ...esigner IDS Software Options section Go to the Options menu on the IDS Figaro main window and select Options Choose AT40K Bitstream from the topics list 1 Note 1 IDS uses names B0 B31 for CR0 CR31 for...

Страница 11: ...pin an input which controls the global tri state control for all user I O CR7 0 8 bit data access 1 16 bit Wide data access CR7 is the Wide data control bit Setting this bit immediately enables bits...

Страница 12: ...he fast clocks The clock buffers are enabled and disabled synchronously with the rising edge of the respec tive FCLK signal and stop in a High 1 state Setting one of these bits disables the appropriat...

Страница 13: ...tream is clocked into the device Figure 6 dis plays a sample 8 bit wide bitstream for an AT40K series device Figure 3 Configuration Download State Machine Idle Power on or Manual Reset No Yes No Hold...

Страница 14: ...ach other Each of these areas is known as a window After the control register the device loads the number of configuration windows A single bitstream can have up to 64K windows The minimum data block...

Страница 15: ...gister Once set the configuration claims the upper 8 dual use I O data pins D8 D15 This implies that at the start of a parallel download in which the user wants wide data bandwidth and D8 D15 as user...

Страница 16: ...and compared to the bitstream on a byte by byte basis in the configuration logic Any differences are reported by driving the INIT pin Low The INIT pin will lower two clocks after the miscompare The Ch...

Страница 17: ...nated all config uration pins are released by the configuration logic and the configuration state returns to Idle A bad preamble causes the INIT pin to be driven Low and causes the bitstream to be ter...

Страница 18: ...in system level integration AT40K series devices have available a number of bits in the control register which cause the I O pins to tri state the Global Set Reset network to activate Low and the Glob...

Страница 19: ...al after CON is driven Low The nets are forced High for glitch less suppression of activity 2 User I O are tri stated on the first rising edge of CCLK after CON has been driven Low CCLK CON GLOBAL SET...

Страница 20: ...LY TRI STATED DURING CONFIGURATION GLOBAL SET RESET NET 3 GCLK 1 FCLK 1 INTERNAL CLOCK NET USER CONTROL OPTIONALLY FORCED ON LOW DURING CONFIGURATION OPTIONALLY DISABLED DURING CONFIGURATION tHGF USER...

Страница 21: ...At the end of power on reset or manual reset CON is not pulsed High For the AT40K series devices either the RESET or INIT pin is tied to the Configurator OE RESET pin and CON is tied to the Configura...

Страница 22: ...Serial Start of Auto configuration Download Note 1 Parameter tOE is taken from the AT17 series datasheet 50K PULL UP INTERNAL tPCCLK tICCLK 20K PULL UP INTERNAL tOE 1 tHCD tSCD BITSTREAM BIT 0 BIT 1 B...

Страница 23: ...ly but the FPGA will not claim the configuration interface until after the first ris ing edge of CCLK after CON goes Low The D0 pin is a dual use I O but must remain an input in order for re configura...

Страница 24: ...edge of CON to first rising edge of CCLK to start recognition 0 6 1 1 6 s tSCCCLK Setup time for CHECK with respect to rising edge of CCLK at the start of a configuration download 6 10 16 ns tDCI Dela...

Страница 25: ...on with a Mode 1 device serial EEPROM in a cascade chain with a Mode 0 device as the master in the chain Configuration Data Source Serial EEPROM Microprocessor Dedicated Configuration Pins RESET CON M...

Страница 26: ...l use I O pin is required as a chip select to enable the part to claim the con figuration so care must be taken by the user not to use the CS0 pin in such a manner that the part may not be reconfigure...

Страница 27: ...usion if the FPGA does drive the pin Low 2 For configuration interface inputs tDCI indicates the time for the user I O to tri state 3 The pins CSOUT and CHECK are claimed by the configuration interfac...

Страница 28: ...ror shown The proper value is 1 The error is shown for timing purposes only under normal circumstances the bitstream download would terminate prematurely 2 The pins CSOUT and CHECK are claimed by the...

Страница 29: ...CCLK Setup time for CHECK with respect to rising edge of CCLK at the start of a configuration download 6 10 16 ns tDCI Delay from rising edge of CCLK to activation of configuration interface at the st...

Страница 30: ...ed CON is released by the FPGA indicating the device is completely ready for user operation Configuration time depends on the frequency of the external clock driving CCLK The maximum frequency in whic...

Страница 31: ...usion if the FPGA does drive the pin Low 2 For configuration interface inputs tDCI indicates the time for the user I O to tri state 3 The pins CSOUT and CHECK are claimed by the configuration interfac...

Страница 32: ...led 1000 ns tSCC Setup time for CON with respect to rising edge of CCLK 6 10 16 ns tSCD Setup time for data with respect to rising edge of CCLK 6 10 16 ns tHCD Hold time for data with respect to risin...

Страница 33: ...ation time depends on the frequency of the external clock driving CCLK The maximum frequency in which a Mode 6 device can be downloaded is 33 MHz A full bitstream for the AT40K20 can be downloaded in...

Страница 34: ...w 2 For configuration interface inputs tDCI indicates the time for the user I O to tri state 3 The pins CSOUT and CHECK are claimed by the configuration interface only if enabled by the control regist...

Страница 35: ...a with respect to rising edge of CCLK 6 10 16 ns tHCD Hold time for data with respect to rising edge of CCLK 0 0 0 ns tSCCCLK Setup time for CHECK with respect to rising edge of CCLK at the start of a...

Страница 36: ...y downstream from a Mode 6 device see Figure 22 Configuration Data Source Microprocessor Parallel EEPROM EPROM PROM Dedicated Configuration Pins RESET CON M0 M1 M2 CCLK Dual use I O D0 D7 INIT LDC HDC...

Страница 37: ...15 shows the config uration timing specifications pertaining to these timing diagrams Note that all D0 D7 inputs for the FPGAs in the cascade chain are tied in parallel The upstream device does not ac...

Страница 38: ...drive the pin Low 2 For configuration interface inputs tDCI indicates the time for the user I O to tri state 3 The pins CSOUT and CHECK are claimed by the configuration interface only if enabled by t...

Страница 39: ...igure 25 Cascade Chain Interface Timing Diagram 1 Notes 1 Cascade bitstream is formed by simple concentration of upstream and downstream bitstreams 2 INIT of upstream and downstream devices are tied t...

Страница 40: ...edge of CCLK 0 0 0 ns tSCCCLK Setup time for CHECK with respect to rising edge of CCLK at the start of a configuration download 6 10 16 ns tDCI Delay from rising edge of CCLK to activation of configu...

Страница 41: ...3551 FAX 81 3 3523 7581 Memory Atmel Corporate 2325 Orchard Parkway San Jose CA 95131 TEL 1 408 436 4270 FAX 1 408 436 4314 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose CA 95131 TEL...

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