5
AT40K Series Configuration
1009B–FPGA–03/02
LDC
LDC is the FPGA “Low During Configuration” pin. It is an output driven Low by the
FPGA during power-on-reset, manual reset, and configuration download. During config-
uration idle, the pin is a fully functional user I/O.
Note:
All user I/O pull-ups and put-downs are programmed by the user. The LDC pin transitions
from driving a strong “0” to a weak “1” after reset. The LDC pin will transition from driving
a strong “0” to the user programmed state at the end of configuration download. If not
programmed, the default state is input with pull-up.
D
0
D
0
is the lsb of the FPGA configuration data bus used to download configuration data to
the device. During power-on-reset or manual reset, D
0
is controlled by the configuration
SRAM. The D
0
pin will transition from the user programmed state to a CMOS input with
a nominal 20K internal pull-up resistor as the SRAM at that location is cleared by the
configuration clear cycle. D
0
becomes an input during configuration download.
D
1
:D
7
D
1
:D
7
are the upper 7 bits of the 8-bit parallel data bus used to download configuration
data to the device. During power-on-reset or manual reset, D
1
:D
7
are controlled by the
configuration SRAM. The D
1
:D
7
pins will transition from the user programmed state to
CMOS inputs with nominal 20K internal pull-up resistors as the SRAM at those locations
is cleared by the configuration clear cycle. When in Modes 2 or 6, D
1
:D
7
become inputs
during configuration download. D
1
:D
7
are not used in the serial Modes 0, 1 and 7.
D
8
:D
15
D
8
:D
15
are the upper 8 bits of the 16-bit parallel wide data bus used to download config-
uration data to the device. During power-on-reset or manual reset, D
8
:D
15
are controlled
by the configuration SRAM. The D
8
:D
15
pins will transition from the user programmed
state to CMOS inputs with nominal 20K internal pull-up resistors as the SRAM at those
locations is cleared by the configuration clear cycle. When in Modes 2 or 6, D
8
:D
15
become optional inputs during configuration download. They become available as soon
as the appropriate bit in the configuration control register is set. D
8
:D
15
are not used in
the serial Modes 0, 1 and 7.
A
0
:A
19
A
0
:A
19
are used to control external addressing of memories during downloads. During
power-on-reset or manual reset, A
0
:A
19
are controlled by the configuration SRAM. The
A
0
:A
19
pins will transition from the user programmed state to CMOS inputs with nominal
20K internal pull-up resistors as the SRAM at those locations is cleared by the configu-
ration clear cycle. When in Mode 6, A
0
:A
19
become outputs during configuration
download. A
0
:A
19
are used only in Mode 6.
Note:
1. Pin A
2
is also pin CS
1
, which is available only for Mode 2. See the description for CS
1
on page 5 for more details.
CS
0
CS
0
is an FPGA configuration chip select. It is active Low. During power-on-reset or
manual reset, CS
0
is controlled by the configuration SRAM. The CS
0
pin will transition
from the user programmed state to a CMOS input with a nominal 20K internal pull-up
resistor as the SRAM at that location is cleared by the configuration clear cycle. In Mode
1, it is used as a chip select to enable configuration to begin. It is most often used as the
chip select of the downstream device in a cascade chain, and is usually driven by
CSOUT of the upstream device. Releasing CS
0
during configuration causes the Mode 1
FPGA to abort the download and release CON. CS
0
is used only in Mode 1.
CS
1
CS
1
is an FPGA configuration chip select. It is active Low. During power-on-reset or
manual reset, CS
1
is controlled by the configuration SRAM. The CS
1
pin will transition
from the user programmed state to a CMOS input with a nominal 20K internal pull-up
