6
AT40K Series Configuration
1009B–FPGA–03/02
resistor as the SRAM at that location is cleared by the configuration clear cycle. In Mode
2, it is used as a chip select to enable configuration to begin. It is most often used as the
chip select of the downstream device in a cascade chain, and is usually driven by
CSOUT of the upstream device. Releasing CS
1
during configuration causes the Mode 2
FPGA to abort the download and release CON. CS
1
is used only in Mode 2.
Note:
1. Pin
CS
1
is also pin A2, which is active only for Mode 6. See the description for A
0
:A
19
,
on page 5 for more details.
CSOUT
CSOUT is the configuration pin used to enable the downstream device in a cascade
chain. During power-on-reset or manual reset, CSOUT is controlled by the configuration
SRAM. The CSOUT pin will transition from the user programmed state to a CMOS input
with a nominal 20K internal pull-up resistor as the SRAM at that location is cleared by
the configuration clear cycle. During configuration download, CSOUT becomes an
optional output. It is enabled by default after reset, and may be enabled or disabled via
the configuration control register. If the user has disabled the cascade function, the pin
remains a user I/O. If the cascade function is enabled, the CSOUT pin is driven High at
the start of configuration download. At the end of the device’s portion of the cascade bit-
stream, the CSOUT pin is driven Low (and into the CS
0
or CS
1
of the downstream
device) to enable the downstream device. CSOUT is released by the device at the end
of the cascade bitstream and becomes a fully functional user I/O.
CHECK
CHECK is a configuration control pin used to control the Check Function. The Check
Function takes a bitstream and compares it to the contents of a previously loaded bit-
stream and notifies the user of any differences. Any differences causes the INIT pin to
go Low. During power-on-reset or manual reset, CHECK is controlled by the configura-
tion SRAM. The CHECK pin will transition from the user programmed state to a CMOS
input with a nominal 20K internal pull-up resistor as the SRAM at that location is cleared
by the configuration clear cycle. During configuration download, CHECK becomes an
optional input. It is enabled by default after reset, and may be enabled or disabled via
the configuration control register. If the user has disabled the Check Function, the pin
remains a user I/O.
OTS
OTS is an input pin used to immediately tri-state all user I/O. It is enabled by a bit in the
configuration control register. Once activated, it is always an input. The OTS tri-state
control of Dual-use pins is superseded by the configuration logic’s claim on those pins. If
the user has disabled the OTS function, the pin remains as User I/O.
Dual-use I/O
Any pin which functions as user I/O and configuration I/O is a dual-use I/O pin. INIT,
HDC, LDC, D
0
:D
15
, A
0
:A
19
, CS
0
, CS
1
, CSOUT, CHECK, and OTS are all dual-use I/O
pins. It must be noted that while the configuration logic controls dual-use I/O pins during
a particular mode of operation, the configuration logic does not control the pull-up, pull-
down, CMOS/TTL threshold select, or Schmitt trigger selects. The user must be cau-
tioned to avoid possible system problems with the use of dual-use I/O pins. For
example, turning off the internal pull-up resistor for the open drain INIT pin would not
apply the weak High required of an open drain driver. Conversely, disabling the pull-up
and enabling the pull-down of the HDC pin might be a good idea, since the user may
then actually see the pin go Low at the end of configuration.
Dual-use pins share input buffers. It should be noted that even when the configuration
has claimed a pin for its own purposes, the user input buffer is still fully functional. This
implies that any user logic tied to the input buffers of the pins in question will remain
operational, see Figure 1.
