13
AT40K Series Configuration
1009B–FPGA–03/02
Configuration
Downloads
The initiation of the writing, reading, or checking design specific data into the FPGA con-
figuration SRAM is called configuration download. Configuration downloads are
executed by a synchronous state machine that controls the flow of data into the FPGA
(Figure 3). The state machine is clocked by CCLK. On the rising edge of each CCLK a
bit or byte of the configuration data bitstream is clocked into the device. Figure 6 dis-
plays a sample 8-bit wide bitstream for an AT40K series device.
Figure 3.
Configuration Download State Machine
Idle
Power on or Manual Reset
No
Yes
No
Hold Con Low
Claim Configuration Interface
No
Load Control Register
> 0
Configuration Clear Cycle
Yes
Cs*n = 0 ?
Mode ?
0
1, 2
6,7
No
Preamble Error?
No
Memory Lockout?
Load Number of Windows
Number of Windows ?
Decrement Window Count
Load Start/End Addresses
Bad Address?
No
Load Data
Address = End ?
No
Yes
= 0
Increment Address
Release Con
Release Configuration Interface
Drive Initn/Errn Low
Yes
Yes
Yes
Yes
Cascading ?
Yes
Drive Csoutn Low
Con = 1 ?
Yes
No
Mode 0 ?
Con = 0 ?
