37
AT40K Series Configuration
1009B–FPGA–03/02
Figure 22.
Cascade 6 2 2 Parallel EEPROM
In Mode 2, CCLK is driven by an external device. On the rising edge of each CCLK, par-
allel data is clocked into the FPGA. To begin configuration, CON and the chip select
(CS
1
) must be driven Low. Once the bitstream is completed, CON is released, indicating
the device is completely ready for user operation. Configuration time depends on the
frequency of the external clock driving CCLK. The maximum frequency in which a Mode
2 device can be downloaded is 33 MHz. A full bitstream for the AT40K20 can be down-
loaded in only 0.30 ms (30 ns per word of configuration data). Any bitstream errors
cause the INIT pin to drive Low. Figure 23 shows the timing of the configuration inter-
face after manually initiating a configuration download from the idle state (without reset).
Figure 24 shows the timing of the configuration interface at the end of configuration
download. Figure 25 shows the timing of the configuration interface at the interface of
the upstream and downstream devices in the cascade chain. Table 15 shows the config-
uration timing specifications pertaining to these timing diagrams.
Note that all D
0
:D
7
inputs for the FPGAs in the cascade chain are tied in parallel. The
upstream device does not accept data intended for downstream devices and propagate
it to the next device; instead, it simply passes a chip select downstream. Note that
CSOUT of the upstream device is connected to the CS
1
of the downstream device.
CS
1
is a dual-use I/O pin required as a chip select to enable the part to claim the config-
uration interface. Care must be taken by the user not to use the CS
1
pin in such a
manner that the part may not be reconfigured. As an example, if the user programs CS
1
as an output driving High, then CS
1
cannot be lowered, and the part will never reconfig-
ure without first either powering down or manually resetting. It is recommended
therefore that for Slave Parallel Mode, the user leave CS
1
as an input.
M0
M1
M2
OTS
CHECK
CCLK
DATA <0:7>
RESET
INIT
CON
CSOUT
AT40K
Mode 6
Slave Parallel Low
ADDR<0:19>
VSS
VDD
Optional IO
Optional IO
M0
M1
M2
OTS
CHECK
CCLK
CS1
DATA <0:7>
RESET
INIT
CON
CSOUT
AT40K
Mode 2
Slave Parallel
M0
M1
M2
OTS
CHECK
CCLK
CS1
DATA <0:7>
RESET
INIT
CON
CSOUT
AT40K
Mode 2
Slave Parallel
ADDR<0:14>
IO<0:7>
OE
CE
AT28C512
VDD
VSS
VDD
VSS
INIT
RESET
CON
CLOCK
