102
M
M
X
X
3
3
6
6
/
/
M
M
X
X
3
3
6
6
L
L
O
O
n
n
l
l
i
i
n
n
e
e
M
M
a
a
n
n
u
u
a
a
l
l
AW
A
R
D
BI
OS
S
e
tu
p
Advanced Chipset Features > Bank 0/1, 2/3 DRAM Timing
Bank 0/1, 2/3 DRAM Timing
SDRAM 8/10ns (Default)
Normal
Medium
Fast
Turbo
This item controls timing point for latching SDRAM data. We
recommend you leave on the default setting value.
Advanced Chipset Features > SDRAM Cycle Length
SDRAM Cycle
Length
2
3 (Default)
This option controls the latency between SDRAM read command
and the time that the data actually becomes available. If you system
has unstable problem, please change the setting from 2 to 3.
Advanced Chipset Features > DRAM Clock
DRAM Clock
Host Clock (Default)
Host+33M
Host-33M
This item allows you selecting DRAM working clock to Host clock,
Host-33MHz or Host+33MHz..
