Unified Fieldbus Controller UFC100-L2 – Basic mode operation
Page 39
Rev. 1.0
Proprietary and confidential information of Aniotek Inc.
21 May 2018
9.
If there was an error then first read FIFO status register (0x0C) and then Error status register (0x05) to find the
reason for the error. Clear the FIFO status register by writing ‘1’ to CRF and CTF in FIFO control register (0x0B).
10.
Compare the received data bytes with transmitted bytes to verify that the correct frame was received.
6.4.2
Using DMA access to the FIFO
The DMA access can only be used for transmission. The reception has to be done by polling RFRY.
1.
Setup a buffer in the memory to store data bytes to be transmitted and another buffer to store the received data bytes.
2.
Set FDP in Mode register (0x01) to ‘1’ to enable Full-duplex mode. Note that this register may have been set to non-
zero value during initialization.
3.
Clear the FIFO status register by writing ‘1’ to CRF and CTF in FIFO control register (0x0B).
4.
Write the number of bytes to be transmitted in Transmit frame length register (0x08, 0x09).
5.
Setup DMA controller to write the number of bytes equal to the value written in step 4.
6.
Write 0xC4 to Control register (0x02) (DMA, RE and TRON are set to ‘1’). Note that the Receiver is enabled.
7.
Poll Interrupt status register and Status register. If RFRY is ‘1’ then read the byte from the FIFO data. If TED is ‘1’
then it is the end of successful transmission. If RED is ‘1’ then it is the end of successful reception and stop polling.
If ERS is ‘1’ then it indicates an error.
8.
If there was an error then first read FIFO status register (0x0C) and then Error status register (0x05) to find the
reason for the error. Clear the FIFO status register by writing ‘1’ to CRF and CTF in FIFO control register (0x0B).
9.
Compare the received data bytes with transmitted bytes to verify that the correct frame was received.
6.5
Watch timer
This procedure is used to test Watch-timer and also check that the INTn signal is working.
1.
Transmit a frame using the procedure in 6.3.
2.
After transmission setup Watch-timer interrupt by writing 0xBF to Interrupt mask register (0x06).
3.
Set IE in Control register (0x02) to ‘1’.
4.
Wait for a duration which is longer than 256 x (value in Watch-time register) microseconds.
5.
Check that INTn becomes low.
6.
Poll Interrupt register and check that RTI becomes ‘1’.
Note that when Interrupt register is read, RTI will be reset to ‘0’ and INTn will become high.
If this procedure – transmission of a frame and waiting for Watch-timer interrupt, is put in a loop then you can use
oscilloscope to monitor INTn. Also check that the gap between two transmissions is equal to 128 x (value in GAP time
register) µs.
6.6
Token timer
The Token timer does not affect the external hardware and thus it is not required to test the hardware. Its operation can be
tested by using the procedure described below.
1.
Write a value larger than the transmission frame length in byte to Token counter (0x18, 0x19). Since it is 16-bit
value a much larger value can be written. Note that the least significant byte (0x18) has to be written first.
2.
Transmit a frame using the procedure in 6.3.
3.
After transmission write ‘1’ to LTR in Timer control register (0x1A).
4.
Read Token counter (0x18, 0x19) and check that its value is approximately equal to (initial value – number of byte
transmitted – 5). The subtraction of ‘5’ is for Preamble (1 byte), Start Delimiter, FCS (2 bytes) and End Delimiter.
