Aniotek UFC100-L2, Руководство пользователя

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Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 17
Rev. 1.0 Proprietary and confidential information of Aniotek Inc. 21 May 2018
3 E
XTERNAL
I
NTERFACES
The UFC100-L2 operates at 2.7 – 3.6 volts. All inputs and outputs require that the voltage does not exceed power supply
voltage.
The external interface signals are divided into following groups:
Clock input,
CPU Bus,
MAU, and
Others.
3.1 Clock Input
The UFC100-L2 can work at clock rate of 1, 2, 4 or 8 MHz.
3.2 CPU Bus Interface
The UFC100-L2 has 8-bit wide data bus and 5 bit address bus interface. It can be connected to most of the CPU types
without any ‘glue’ logic. It always indicates the completion of the access on ‘RDY / DACKn’ output pin.
1. If the CPU uses multiplexed address and data lines, then the external circuit has to use a latch to store the address.
2. It always indicates the completion of the access on ‘RDY / DACKn’ output pin. A CPU does not have to use ‘RDY /
DACKn’ signal, if it can be programmed with wait states. The worst case cycle time is four (4) periods of CLKIN
input.
3. If the CPU uses a bus that runs at a higher clock rate than CLKIN input of UFC100-L2 and if the CPU cannot use
‘RDY / DACKn’ signal and if the CPU cannot insert enough wait states, then it has to use software to poll a status
bit (ARDY) inside UFC100-L2. This bit indicates that it is ready for next cycle.
4. The inputs A6 and A5 can be connected to ‘0’. These addresses are not used.
5. If the microcontroller does not support DMA, then do not connect RQ output.
6. If the microcontroller supports DMA or DMA controller is available, then use RQ. This output has one pulse for
each byte to be transferred. The active polarity of this pulse is high.
7. The reset input can be connected to either an output port of the microcontroller or its reset input.
Table 17: CPU Bus type connections
CTYP
(pin 37)
ATYP
(pin 38)
CPY type Description
0 0 Intel Pin 2 is RDn – Read Strobe, active low.
Pin 3 is WRn – Write Strobe, active low.
Pin 27 is RDY – a high indicates the cycle can be completed.
0 1 Intel Pin 2 is RDn – Read Strobe, active low.
Pin 3 is WRn – Write Strobe, active low.
Pin 27 is DACKn – a low indicates the cycle can be completed.
1 0 Freescale Pin 2 is E – a high indicates start of the active part of the cycle.
Pin 3 is RWn – a high indicates Read cycle.
Pin 27 is RDY – a high indicates the cycle can be completed.
1 1 Freescale Pin 2 is DSn – a low indicates start of the active part of the cycle.
Pin 3 is RWn – a high indicates Read cycle.
Pin 27 is DACKn – a low indicates the cycle can be completed.