Unified Fieldbus Controller UFC100-L2 – Basic mode operation
Page 38
Rev. 1.0
Proprietary and confidential information of Aniotek Inc.
21 May 2018
8.
Poll ERS and TED in the Interrupt status register (0x04). If TED is ‘1’ then it is the end of successful transmission.
If ERS is ‘1’ then there was an error.
9.
If there was an error then first read FIFO status register (0x0C) and then Error status register (0x05) to find the
reason for the error. Clear the FIFO status register by writing ‘1’ to CTF in FIFO control register (0x0B).
You can use an oscilloscope to check that the frame was transmitted. If RxA input was ‘1’ before starting the
transmission then the UFC waits until RxA becomes ‘0’ before starting the transmission. Since the MAU itself receives
the transmitted signal, the RxA input to the UFC100-L2 should be ‘1’ during the transmission after a delay. If RxA
remain ‘0’ during the transmission then it is considered an error, CNS in Error status register is set to ‘1’ and the
transmission is aborted.
You can deliberately cause error such as underrun to test error handling.
6.3.2
Using DMA Write to the Transmit FIFO
1.
Setup a buffer in the memory to store data bytes to be transmitted. Keep the data pattern such that any shorts in the
data bus can be detected. For example 256 bytes with value from 0x00 to 0xFF can be stored.
2.
Write to Mode register if necessary to update LB, FDP, PRE and TFCS. Note that this register may have been set to
non-zero value during initialization.
3.
Clear the FIFO status register by writing ‘1’ to CTF in FIFO control register (0x0B).
4.
Write the number of bytes to be transmitted in Transmit frame length register (0x08, 0x09).
5.
Setup DMA controller to Write the number of bytes equal to the value written in step 4.
6.
Write 0x84 to Control register (0x02) (DMA and TRON are set to ‘1’). Note that the Receiver is disabled.
7.
Poll ERS and TED in the Interrupt status register (0x04). If TED is ‘1’ then it is the end of successful transmission.
If ERS is ‘1’ then there was an error.
8.
If there was an error then first read FIFO status register (0x0C) and then Error status register (0x05) to find the
reason for the error. Clear the FIFO status register by writing ‘1’ to CTF in FIFO control register (0x0B).
The DMA transfer starts as soon as TRON is set to ‘1’.
6.4
Frame reception
It is necessary to send a frame to the device under test. This can be done either by an external source or by transmitting the
frame and receiving it in the same device. The internal loopback is not used so that external MAU can be tested. The
procedure for transmitting and receiving one frame is described. It should be used for testing the hardware including
UFC100-L2 and external MAU. The product software may use slightly different procedure e.g. it may use Half-duplex.
These procedures do not use interrupt.
6.4.1
Using non-DMA access to the FIFO
1.
Setup a buffer in the memory to store data bytes to be transmitted and another buffer to store the received data bytes.
2.
Set FDP in Mode register (0x01) to ‘1’ to enable Full-duplex mode. Note that this register may have been set to non-
zero value during initialization.
3.
Clear the FIFO status register by writing ‘1’ to CRF and CTF in FIFO control register (0x0B).
4.
Write the number of bytes to be transmitted in Transmit frame length register (0x08, 0x09).
5.
Write few bytes in the FIFO data register (0x0D), so that delay in software loop does not cause underrun.
6.
Write 0x44 to Control register (0x02) (RE and TRON are set to ‘1’). Note that the Receiver is enabled.
7.
Poll TFRY and RFRY in Status register (0x03). As long as TFRY is ‘1’ another byte can be written to the FIFO
data. If RFRY is ‘1’ then the received data byte can be read from the FIFO data and stored in the memory buffer.
Write all of the bytes in the frame to be transmitted. The number of bytes to be written in step 5 and this step has to
be equal to the value written in the step 4. Otherwise, underrun or TLM error occurs.
8.
Poll Interrupt status register and Status register. If RFRY is ‘1’ then read the byte from the FIFO data. If RED is ‘1’
then it is the end of successful reception and stop polling. If ERS is ‘1’ then it indicates an error.
