Unified Fieldbus Controller UFC100-L2 – Basic mode operation
Page 37
Rev. 1.0
Proprietary and confidential information of Aniotek Inc.
21 May 2018
6 T
EST PROCEDURES
The procedures to test the hardware are described. These procedures can also be used in device driver with some changes to
suit the product software.
6.1
Register access
If the hardware interface to the CPU uses RDY signal, then the registers can be accessed as memory locations. If the RDY is
not used, but Read and Write cycles are at least 4 cycles of the CLKIN input to the UFC100-L2, the registers can be accessed
as memory locations. Else, the software should poll ARDY from Status register; and it should Read or Write only if ARDY is
‘1’.
6.2
Initialization
The UFC100-L2 requires following settings before it can be used for transmission or reception.
1.
Write 0x80 to Reset register (0x00).
2.
Write to Mode register (0x01). The value depends upon the frequency of the clock input. The internal clock has to
be 500 kHz – see CLOCK in 2.2.4. Set other fields as following:
LB = 0, FDP = 1 (for test purpose), PRE = 1 (for test purpose), TFCS = 0, TMD = 0 (assuming using MAU with
Enable mode).
3.
Write to Interrupt mask (0x06) and Error mask (0x07) registers to enable interrupt, if required.
4.
Write to FIFO control register (0x0B) according to software need. For transmission, it is better to set high threshold.
For reception, it is better to set low threshold, so that the incoming frame FC and address can be checked. After
checking these two bytes in the received frame, it is better to set high threshold to reduce the interrupts. For
hardware test, use any threshold setting.
5.
Write to GAP time register (0x14). The value depends upon the Data Link layer configuration. For test purpose, set
it to 0x10 (8 bytes).
6.
Write to Watch time register (0x16, 0x17). The value depends upon the Data Link layer configuration. For test
purpose, set it to 0x20 (32 bytes).
7.
Clear Watch-timer by writing 0x02 to Timer control register (0x1A).
6.3
Frame transmission
The procedure for transmitting one frame is described. It should be used for testing the hardware including UFC100-L2 and
external MAU. The product software may use slightly different procedure e.g. it may use Half-duplex. These procedures do
not use interrupt.
6.3.1
Using non-DMA Write to the Transmit FIFO
1.
Setup a buffer in the memory to store data bytes to be transmitted. Keep the data pattern such that any shorts in the
data bus can be detected. For example 256 bytes with value from 0x00 to 0xFF can be stored.
2.
Write to Mode register if necessary to update LB, FDP, PRE and TFCS. Note that this register may have been set to
non-zero value during initialization.
3.
Clear the FIFO status register by writing ‘1’ to CTF in FIFO control register (0x0B).
4.
Write the number of bytes to be transmitted in Transmit frame length register (0x08, 0x09).
5.
Write few bytes in the FIFO data register (0x0D), so that delay in software loop does not cause underrun.
6.
Write 0x04 to Control register (0x02) (TRON is set to ‘1’). Note that the Receiver is disabled.
7.
Poll TFRY in Status register (0x03). As long as this is ‘1’ another byte can be written to the FIFO data. Write all of
the bytes in the frame to be transmitted. The number of bytes to be written in step 5 and this step has to be equal to
the value written in the step 4. Otherwise, underrun or TLM error occurs.
