ADSP-21065L SHARC User’s Manual 1-7
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High Level Languages
. The ADSP-21065L’s architecture has several fea-
tures that directly support high-level language compilers and operating
systems:
• General purpose data and address register files.
• 32-bit native data types.
• Large address space.
• Pre- and postmodify addressing.
• Unconstrained circular data buffer placement.
• On-chip program, loop, and interrupt stacks.
Additionally, the ADSP-21065L architecture is designed specifically to
support ANSI-standard Numerical C extensions—the first compiled lan-
guage to support vector data types and operators for numeric and signal
processing.
Serial Scan and Emulation Features
. The ADSP-21065L supports the
IEEE standard P1149.1 Joint Test Action Group (JTAG) standard for
system test. This standard defines a method for serially scanning the I/O
status of each component in a system. The ADSP-21065L EZ-ICE
in-circuit emulator also uses the JTAG serial port to access the processor’s
on-chip emulation features.
IEEE Formats
. The ADSP-21065L supports IEEE floating-point data for-
mats. This means that algorithms developed on IEEE-compatible
processors and workstations are portable across processors without con-
cern for possible instability introduced by biased rounding or inconsistent
error handling.
