ADSP-21065L SHARC User’s Manual 1-3
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Figure 1-2
, a detailed block diagram of the processor, shows its architec-
tural features.
Figure 1-2. ADSP-21065L block diagram
Figure 1-2
also shows the ADSP-21065L’s on-chip buses: the PM (Pro-
gram Memory) bus, made up of the PMA (Program Memory Address) and
PMD (Program Memory Data) buses; the DM (Data Memory) bus, made
up of the DMA (Data Memory Address) and DMD (Data Memory Data)
buses; and the I/O bus, made up of the IOA (I/O Address) and IOD (I/O
Data) buses.
The PM bus can access either instructions or data. During a single cycle,
the processor can access two data operands, one over the PM bus and one
over the DM bus, access an instruction from the cache, and perform a
DMA transfer.
The ADSP-21065L’s external port provides the processor’s interface to
external memory, which is glueless to an SDRAM; memory-mapped I/O;
DATA
ADDR
DATA
ADDR
BLOCK 1
T
WO
I
NDEPENDENT
D
UAL
-P
ORTED
B
LOCKS
PROCESSOR
PORT
I/O
PORT
ADDR
DATA
DATA
ADDR
BLOCK 0
IOP
Registers
Control,
Status, Timer,
&
Data Buffers
DMA
Controller
SPORT 0
SPORT 1
SDRAM Interface
HOST Port
Addr Bus
Mux
Data Bus
Mux
4
Multiprocessor
Interface
DAG1
8x4x32
DAG2
8x4x24
Program
Sequencer
Instruction
cache
32x48b
Bus
Connect
(PX)
Multiplier
Barrel
Shifter
ALU
Data
Register
File
16x40b
24
32
48
40
PM Address Bus
DM Data Bus
PM Data Bus
DM Address Bus
7
JTAG
Test &
Emulation
IOD
48
IOA
17
24
32
(2 Rx, 2 Tx)
(2 Rx, 2 Tx)
(I2S)
(I2S)
I/O Processor
DSP Core
Dual-Ported SRAM
External Port
