ADSP-21065L SHARC User’s Manual 1-17
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The ADSP-21065L’s external port provides the processor’s interface to
off-chip memory and peripherals. The 64M
×
32-bit word, off-chip
address space is included in the ADSP-21065L’s unified address space.
The separate on-chip buses—for PM addresses, PM data, DM addresses,
DM data, I/O addresses, and I/O data—are multiplexed at the external
port to create an external system bus with a single 24-bit address bus and a
single 32-bit data bus.
The ADSP-21065L provides an on-chip SDRAM controller that supports
a glueless interface to standard 16Mb and 64Mb SDRAMs.
The on-chip decoding of high-order address lines to generate memory
bank select signals facilitates the addressing of external memory devices.
The ADSP-21065L provides programmable memory wait states and exter-
nal memory acknowledge controls to enable the processor to interface
with peripherals with variable access, hold, and disable time requirements.
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The ADSP-21065L’s host interface provides a connection to standard 8-,
16-, or 32-bit microprocessor buses that is easy and requires little addi-
tional hardware.
The ADSP-21065L supports asynchronous transfers at speeds up to the
processor’s full clock rate. The ADSP-21065L’s external port provides
access to the processor’s host interface, which is memory-mapped into the
processor’s unified address space.
Two channels of DMA are available for the host interface, and they per-
form code and data transfers with low software overhead. The host can
directly read and write the IOP registers of the ADSP-21065L and can
access the DMA channel setup and mailbox registers.
