Analog Devices SHARC ADSP-21065L Скачать руководство пользователя

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1-24 ADSP-21065L SHARC User’s Manual

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Figure 1-4

shows how the ADSP-21065L’s design optimally balances its

high-performance DSP core with its high-speed I/Os.

Figure 1-4. Balanced performance between the DSP core and I/O

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The following publications can be ordered from any Analog Devices sales
office.

ADSP-21000 Family Hardware & Software Development Tools

Data Sheet

ADSP-21065L SHARC Data Sheet
C Compiler Guide and Reference for the ADSP-2106x Family DSPs
Debugger Tutorial for the ADSP-2106x Family DSPs
VisualDSP Debugger Guide and Reference
VisualDSP Release Notes
VisualDSP User’s Guide and Reference

ADSP-21065L

60 MHz

ADSP-21065L

60 MHz

Host

Micro

SDRAM

SRAM

CLK

30 MHz

Codec

30 Mbits/s

240 Mbytes/s

120 Mbytes/s

Содержание SHARC ADSP-21065L

Страница 1: ...every instruction in a single cycle The ADSP 21065L is code compatible with other members of the SHARC family Four independent buses for dual data instructions and I O and cross bar switch memory conn...

Страница 2: ...general pur pose I O ports JTAG test access port Figure 1 1 shows the ADSP 21065L s Super Harvard Architecture which consists of a crossbar bus switch connecting the DSP core s numeric pro cessor to...

Страница 3: ...s and one over the DM bus access an instruction from the cache and perform a DMA transfer The ADSP 21065L s external port provides the processor s interface to external memory which is glueless to an...

Страница 4: ...l signals to shared global memory and I O devices The documentation set ADSP 21065L SHARC User s Manual and ADSP 21065L SHARC Technical Reference contain ADSP 21065L archi tectural information and the...

Страница 5: ...ddition subtraction and combined multiplication addi tion it also provides a complete set of arithmetic operations including Seed 1 X Seed 1 X Min Max Clip Shift and Rotate The ADSP 21065L is IEEE flo...

Страница 6: ...l Address Generators The ADSP 21065L has two data address gener ators DAGs that provide immediate or indirect pre and postmodify addressing It supports modulus and bit reverse operations with no con s...

Страница 7: ...an guage to support vector data types and operators for numeric and signal processing Serial Scan and Emulation Features The ADSP 21065L supports the IEEE standard P1149 1 Joint Test Action Group JTAG...

Страница 8: ...rithm development is to unconstrain the regularity and dynamic range of intermediate results Adaptive filtering and imaging are two applications that require a wide dynamic range Signal to Noise Ratio...

Страница 9: ...emory External port interface Host processor interface I O Processor Serial ports DMA controller Booting Development tools The remaining chapters of this manual describe these features in detail 63 RU...

Страница 10: ...ard set of arithmetic and logic operations in both fixed point and floating point formats Multiplier with a fixed point accumulator Performs floating point and fixed point multiplication and fixed poi...

Страница 11: ...n units and the data buses and to store intermedi ate results For fast context switching the Register File has two sets primary and alternate of sixteen registers All of the registers are 40 bits wide...

Страница 12: ...operand reads or writes DAG1 supplies 32 bit addresses to data memory DAG2 supplies 24 bit addresses to program memory for program memory data accesses Each DAG keeps track of up to eight address poi...

Страница 13: ...has four buses Program Memory Address Transfers the addresses for instructions Data Memory Address Transfers the addresses for data Program Memory Data Transfers instructions Since the PM Data bus is...

Страница 14: ...ual data registers in the Register File are all universal registers The PX bus connect registers provide the path to pass data between the 48 bit PM Data bus and the 40 bit DM Data bus or between the...

Страница 15: ...s registers have alternate registers that applications can activate and use during interrupt servicing to implement a fast context switch Each of the data registers in the Register File the DAG regist...

Страница 16: ...for 16 bit data 10K words of 48 bit instructions and 40 bit data or combinations of different word sizes up to 544 Kbits All the memory can be accessed as 16 bit 32 bit or 48 bit The ADSP 21065L supp...

Страница 17: ...the addressing of external memory devices The ADSP 21065L provides programmable memory wait states and exter nal memory acknowledge controls to enable the processor to interface with peripherals with...

Страница 18: ...serial ports can operate at the full clock rate of the processor provid ing each with a maximum data rate of 30 Mbit s Each serial port has a primary and a secondary set of Tx and Rx channels as shown...

Страница 19: ...a tions to occur while the core is simultaneously executing its program Applications can use DMA transfers to download both code and data to the ADSP 21065L DMA transfers can occur between the ADSP 21...

Страница 20: ...DSP 21065L with the exception of displaying and modifying the two new SPORTs registers The emulator will not display these two registers but your code can still use them Both the SHARC Development Too...

Страница 21: ...tputs Maintain a one to one correspondence with the tool s command line switches The EZ ICE Emulator uses the IEEE 1149 1 JTAG test access port of the ADSP 21065L processor to monitor and control the...

Страница 22: ...ures and benefits Feature Benefits 32 bit processing More precise processing of 16 bit signals 32 bit words essential for pro cessing 20 and 24 bit input sig nals Improved signal to noise ratio at low...

Страница 23: ...serial Tx and 2 serial Rx serial ports I2S Interface Process more audio channels using just one DSP Multiple channels supported in communication systems 10 DMA channels Implement multifunction applica...

Страница 24: ...s can be ordered from any Analog Devices sales office ADSP 21000 Family Hardware Software Development Tools Data Sheet ADSP 21065L SHARC Data Sheet C Compiler Guide and Reference for the ADSP 2106x Fa...

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