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1-18 ADSP-21065L SHARC User’s Manual
Vector interrupt support provides efficient execution of host commands.
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The ADSP-21065L’s I/O Processor (IOP) includes two serial ports, each
with two transmitters and two receivers, and a DMA controller.
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The ADSP-21065L features two synchronous serial ports that provide an
inexpensive interface to a wide variety of digital and mixed-signal periph-
eral devices.
The serial ports can operate at the full clock rate of the processor, provid-
ing each with a maximum data rate of 30 Mbit/s. Each serial port has a
primary and a secondary set of Tx and Rx channels, as shown in
Figure 1-3
.
Figure 1-3. Serial port input/output configuration
Independent transmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automatically transferred to
and from on-chip memory through DMA. Each of the serial ports sup-
ports three operation modes: standard mode, I
2
S mode (an interface
RX0_A
RX1_A
RX0_B
RX1_B
RFS0
RFS1
RCK0
RCK1
TX0_A
TX1_A
TX0_B
TX1_B
TFS0
TFS1
TCK0
TCK1
SPORTx
