UG-173
Evaluation Board User Guide
Rev. B | Page 8 of 24
CLOCKING WITH INTERLEAVED DATA
ADCs with very high data rates can exceed the capability of a
single buffer memory channel (~133 MSPS). These converters
often demultiplex the data into two channels to reduce the rate
required to capture the data. In these applications, ADC Analyzer
must interleave the data from both channels to process it as a
single channel. The user can configure the software to process
the first sample from Channel A, the second from Channel B,
and so on, or vice versa. The synchronization circuit included in
the buffer memory forces a small delay between the write enable
signals (WENA and WENB) being sent to the FIFO memory chips
(Pin 1, U101, and U201), ensuring that the data is captured in one
FIFO before the other. Jumper J401 and Jumper J402 determine
which FIFO receives WENA and which FIFO receives WENB.
CONNECTING TO THE HSC-ADC-FIFO5-INTZ
ADCs that have serial LVDS outputs require another board, that
is, the HSC-ADC-FIFO5-INTZ, which connects between the
ADC evaluation board and the FPGA-based data capture card,
HSC-ADC-EVALCZ. Refer to the HSC-ADC-EVALCZ data
sheet at
www.analog.com/FIFO
for more detailed information
on this board.
CONNECTING TO THE HSC-ADC-AD922xFFA OR
HSC-ADC-AD9283FFA ADAPTER BOARDS
Older ADC evaluation boards, such as the
AD9203
,
AD9220
,
AD9226
, and
AD9283
, have different pinouts and therefore
require that another board, that is, the HSC-ADC-AD922xFFA
or HSC-ADC-AD9283FFA adapter board, be connected between
the ADC evaluation board and the FIFO data capture card. This
board routes the outputs of the ADC evaluation board to the
correct locations on the FIFO board.
When connecting the HSC-ADC-AD922xFFA or HSC-ADC-
AD9283FFA adapter board, connect the female connector to the
ADC evaluation board, and then connect the male connector to
the FIFO board. Next, ensure that the HSC-ADC-AD922xFFA
or HSC-ADC-AD9283FFA adapter board connects to the data
lines (Row A and Row B) of the FIFO board connector as shown
in Figure 4. Email
for more
detailed information about this board.
CONNECTING TO THE HSC-ADC-DEMUXZ
ADAPTER BOARD
The
AD9480
and
AD9430
ADCs have parallel LVDS outputs
and require another board connected between the ADC evaluation
board and the FIFO data capture card. This board converts parallel
LVDS to parallel CMOS, using both channels of the FIFO data
capture card. Email
for more
detailed information about this board.
CONNECTING ADC EVALUATION BOARDS WITH
DOUBLE ROW CONNECTORS
The HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC (FIFO 4) was
the predecessor to the HSC-ADC-EVALB-DCZ (FIFO 4.1) and
had only an 80-pin, double row input connector. The FIFO 4.1 has
a 120-pin, triple row input connector to allow connection with newer
ADCs that have SPI. Two examples of connecting FIFO 4.1 to an
older style ADC evaluation board are shown in Figure 4 and Figure 5.
05
87
0
-0
0
4
Figure 4. Single-Channel ADC
05
87
0
-0
0
5
Figure 5. Dual-Channel ADC
UPGRADING FIFO MEMORY
The FIFO evaluation board includes two 32 kB FIFOs that are
capable of 133 MHz clock signals. Pin-compatible FIFO upgrades
are available from Integrated Device Technology. See Table 1 for the
IDT part number matrix and visit its website for more information.
Table 1. IDT Part Number Matrix
1
Part Number
FIFO Depth
FIFO Speed
IDT72V283L7-5PF (Default )
32 kB
133 MHz
IDT72V293L7-5PF
64 kB
133 MHz
IDT72V2103L7-5PF
132 kB
133 MHz
IDT72V2113L7-5PF
256 kB
133 MHz
IDT72V283L6PF
32 kB
166 MHz
IDT72V293L6PF
64 kB
166 MHz
IDT72V2103L6PF
132 kB
166 MHz
IDT72V2113L6PF
256 kB
166 MHz
