Evaluation Board User Guide
UG-173
Rev. B | Page 7 of 24
THEORY OF OPERATION
The FIFO evaluation board can be divided into several circuits,
each of which plays an important part in acquiring digital data
from the ADC and allows the PC to upload and process that
data. The evaluation kit is based on the IDT72V283 FIFO chip
from Integrated Device Technology, Inc. (IDT). The system can
acquire digital data at speeds of up to 133 MSPS and data record
lengths of up to 32 kB using the HSC-ADC-EVALB-DCZ, which
has two FIFO chips and is available to evaluate single and multi-
channel ADCs or demultiplexed data from ADCs sampling faster
than 133 MSPS. A USB 2.0 microcontroller communicating with
ADC Analyzer allows for easy interfacing to newer computers
using the USB 2.0 (USB 1.1-compatible) interface.
The process of filling the FIFO chip or chips and reading the data
back requires several steps. First, ADC Analyzer initiates the FIFO
chip fill process. The FIFO chips are reset using a master reset signal
(MRS). The USB microcontroller is then suspended, which turns
off the USB oscillator and ensures that it does not add noise to
the ADC input. After the FIFO chips completely fill, the full
flags from the FIFO chips send a signal to the USB microcontroller
to wake up the microcontroller from suspend. ADC Analyzer waits
for approximately 30 ms and then begins the readback process.
During the readback process, the acquisition of data from
FIFO 1 (U201) or FIFO 2 (U101) is controlled via Signal OEA
and Signal OEB. Because the data outputs of both FIFO chips
drive the same 16-bit data bus, the USB microcontroller controls
the OEA and OEB signals to read data from the correct FIFO chip.
From an application standpoint, ADC Analyzer sends commands
to the USB microcontroller to initiate a read from the correct FIFO
chip, or from both FIFO chips in dual or demultiplexed mode.
CLOCKING DESCRIPTION
Each channel of the buffer memory requires a clock signal to
capture data. These clock signals are normally provided by the
ADC evaluation board and are passed along with the data through
Connector J104 (Pin 37 for both Channel A and Channel B). If
only a single clock is passed for both channels, they can be
connected together by Jumper J303.
Jumpers J304 and J305 at the output of the LVDS receiver allow
the output clock to be inverted by the LVDS receiver. By default,
the clock outputs are inverted by the LVDS receiver.
The single-ended clock signal from each data channel is buffered
and converted to a differential CMOS signal by two gates of a
low voltage differential signal (LVDS) receiver, U301. This allows
the clock source for each channel to be CMOS, TTL, or ECL.
The clock signals are ac-coupled by 0.1 μF capacitors. The R312
and R315 potentiometers allow for fine-tuning the threshold of the
LVDS gates. In applications where fine-tuning the threshold is
critical, these potentiometers can be replaced with a higher
resistance value to increase the adjustment range. Resistors
R301, R302, R303, R304, R311, R313, R314, and R316 set the
static input to each of the differential gates to a dc voltage of
approximately 1.5 V.
At assembly, Solder Jumper J310 to Solder Jumper J313 are
set to bypass the potentiometer. For fine adjustment using the
potentiometers, the solder jumpers must be removed and R312
and R315 must be populated.
U302, an XOR gate array, is included in the design to let users add
gate delays to the clock paths of the FIFO memory chips. They are
not required under normal conditions and are bypassed at assembly
by Jumper J314 and Jumper J315. Jumper J306 and Jumper J307
allow the clock signals to be inverted through an XOR gate. In the
default setting, the clocks are not inverted by the XOR gate.
These clock paths determine the WRT_CLK1 and WRT_CLK2
signals at each FIFO memory chip (U101 and U201). These
timing options should let you choose a clock signal that meets
the setup time and hold time requirements to capture valid data.
A clock generator can be applied directly to S1 and/or S3. This
clock generator should be the same unit that provides the clock
for the ADC. These clock paths are ac-coupled so that a sine
wave generator can be used. DC bias can be adjusted by
R301/R302 and R303/R304.
The DS90LV048A differential line receiver is used to square
the clock signal levels applied externally to the FIFO evaluation
board. The output of this clock receiver can either directly drive
the write clock of the IDT72V283 FIFO(s), or first pass through
the XOR gate timing circuitry previously described.
SPI DESCRIPTION
The Cypress IC (U502) supports the HSC SPI standard to allow
programming of ADCs that have SPI-accessible register maps.
U102 is a buffer that drives the 4-wire SPI (SCLK, SDI, SDO,
CSB) through the 120-pin connector (J104) on the third or top
row. (Note that CSB1 is the default CSB line used.) J502 is an
auxiliary SPI connector that monitors the SPI signals connected
directly to the Cypress IC. For more information on this and
other functions, consult the user manual titled
Interfacing to
High Speed ADCs via SPI
at
www.analog.com/FIFO
.
The SPI interface designed on the Cypress IC can communicate with
up to five different SPI-enabled devices. The CLK and data lines
are common to all SPI devices. The correct device is chosen to
communicate by using one of the five active low chip select pins.
This functionality is controlled by selecting a SPI channel in the
software.
