UG-1135
Rev. 0 | Page 13 of 45
5.
Configure the S/PDIF transmitter (Tx) signal routing as
follows:
a.
Click the
S/PDIF TX
box (see Figure 42).
1
578
9-
0
44
Figure 42. Configuring the S/PDIF Transmitter Routing Matrix Register
b.
From the dropdown menu that appears, select
From
DSP
to choose the signal coming from the DSP core
1
578
9-
045
Figure 43. Routing the DSP Core Outputs to the S/PDIF Transmitter
c.
Close the dialog box shown in Figure 43.
d.
Confirm that the setting has taken effect by verifying that
the color of the
S/PDIF TX
box has changed from gray
to black (see Figure 44). If the color of the box changes
to black, the DSP core has been routed to the S/PDIF
transmitter; therefore, the output of ASRC 0 can be used
in the DSP program.
15
789
-04
6
Figure 44. Confirming that the DSP Core Outputs are Routed
to the S/PDIF Transmitter
6.
Click the
Schematic
tab at the top of the window to return
to the schematic design view.
7.
Add an S/PDIF input to the project as follows:
a.
From the
IO > ASRC > From ASRC
folder, click
Asrc
Input
(see Figure 45) and drag it into the project space
to the right of the toolbox (see Figure 46).
15789-
04
7
Figure 45. ASRC Input Block Selection
15
789
-04
8
Figure 46. ASRC Input Block
Because the left and right signals of the S/PDIF receiver are
passing through the ASRC 0, the input to the DSP program
is the
Asrc Input
. This naming con-
vention is such that all blocks in
are named
from the perspective of the DSP core. Therefore, the
Asrc
Input
block in
represents the input to the DSP
from the ASRC outputs. The inputs to the ASRCs themselves
are defined in the register window (see Figure 41).
By default, Channel 0 and Channel 1 are active when their
corresponding checkboxes are selected. Because the ASRC 0
outputs correspond to Channel 0 and Channel 1, this default
configuration can be used (see Figure 46). For reference, a
mapping of the ASRC outputs to the corresponding channels
on the
Asrc Input
block in the DSP schematic is provided in
Table 1. ASRC Output to
Input Channel Mapping
ASRC Output
Corresponding Channels on ASRC Input
Block in
ASRC 0
Channel 0 and Channel 1
ASRC 1
Channel 2 and Channel 3
ASRC 2
Channel 4 and Channel 5
ASRC 3
Channel 6 and Channel 7
ASRC 4
Channel 8 and Channel 9
ASRC 5
Channel 10 and Channel 11
ASRC 6
Channel 12 and Channel 13
ASRC 7
Channel 14 and Channel 15
Содержание EVAL-ADAU1466Z
Страница 37: ...EVAL ADAU1466Z User Guide UG 1135 Rev 0 Page 37 of 45 15789 087 Figure 96 EVAL ADAU1466Z Layout Top Assembly ...
Страница 38: ...UG 1135 EVAL ADAU1466Z User Guide Rev 0 Page 38 of 45 15789 088 Figure 97 EVAL ADAU1466Z Layout Top Copper ...
Страница 39: ...EVAL ADAU1466Z User Guide UG 1135 Rev 0 Page 39 of 45 15789 089 Figure 98 EVAL ADAU1466Z Layout Ground Plane ...
Страница 40: ...UG 1135 EVAL ADAU1466Z User Guide Rev 0 Page 40 of 45 15789 090 Figure 99 EVAL ADAU1466Z Layout Power Plane ...
Страница 41: ...EVAL ADAU1466Z User Guide UG 1135 Rev 0 Page 41 of 45 15789 091 Figure 100 EVAL ADAU1466Z Layout Bottom Copper ...
