UG-1135
Rev. 0 | Page 12 of 45
To add an S/PDIF input and output to the project in
take the following steps:
1.
Connect an S/PDIF source to the EVAL-ADAU1466Z
evaluation board by using a standard TOSLINK® optical
cable and connecting it to the S/PDIF receiver connector,
U2 (see Figure 33).
1578
9-
0
35
Figure 33. Photograph of the Optical S/PDIF Input Connection
2.
Configure the S/PDIF input and output by modifying the
registers as follows:
a.
Click the
Hardware Configuration
tab, then click the
IC 1 – ADAU146x Register Controls
tab at the
bottom of the window (see Figure 34).
15
789-
036
Figure 34.
IC 1 - ADAU146x Register Controls
Tab
b.
Click the
SPDIF
tab (see Figure 36). There are several
register control tabs listed across the top of the window.
To access the
SPDIF
tab, click the right arrow to scroll
1
578
9-
037
Figure 35. Using the Register Tab Scroll Button
1
5789
-0
38
Figure 36. Selecting the
SPDIF
Tab
c.
Enable the SPDIF_RESTART register by clicking
Do
not restart the audio once a re-lock has occurred
in
the
SPDIF RESTART
box. When this button is clicked,
the text displayed on the button changes to
Restarts
the audio once a re-lock has occurred
and the button
color changes from red to green (see Figure 37).
15
789
-03
9
Figure 37. Activating the SPDIF_RESTART Register
d.
To activate the S/PDIF interface, click
Disabled
in the
SPDIF TX EN
box. When this button is clicked, the text
displayed on the button changes to
Enabled
and the
button color changes from red to green (see Figure 38).
1
5789
-040
Figure 38. Activating the SPDIF_TX_EN Register
3.
Click the
ROUTING_MATRIX
tab (see Figure 39) to
allow the configuration of the routing matrix.
1
5789-
041
Figure 39. Selecting the ROUTING_MATRIX Tab
4.
To configure the S/PDIF receiver signal routing, click the
first asynchronous sample rate converter,
ASRC 0
(see
Figure 40) and configure ASRC 0 using the dropdown menus
until it matches Figure 41. This configuration routes the
S/PDIF receiver signal through an ASRC before it is accessed
in the DSP core. Routing the signal in this way is necessary
because the clock recovered from the S/PDIF source is not
synchronous to the
15789-
042
Figure 40. ASRC 0 Control Button
15789-
043
Figure 41. Configuring the ASRC 0 Routing Matrix Registers
Содержание EVAL-ADAU1466Z
Страница 37: ...EVAL ADAU1466Z User Guide UG 1135 Rev 0 Page 37 of 45 15789 087 Figure 96 EVAL ADAU1466Z Layout Top Assembly ...
Страница 38: ...UG 1135 EVAL ADAU1466Z User Guide Rev 0 Page 38 of 45 15789 088 Figure 97 EVAL ADAU1466Z Layout Top Copper ...
Страница 39: ...EVAL ADAU1466Z User Guide UG 1135 Rev 0 Page 39 of 45 15789 089 Figure 98 EVAL ADAU1466Z Layout Ground Plane ...
Страница 40: ...UG 1135 EVAL ADAU1466Z User Guide Rev 0 Page 40 of 45 15789 090 Figure 99 EVAL ADAU1466Z Layout Power Plane ...
Страница 41: ...EVAL ADAU1466Z User Guide UG 1135 Rev 0 Page 41 of 45 15789 091 Figure 100 EVAL ADAU1466Z Layout Bottom Copper ...
