12 Programming Model
12 – 6
12.1.3
Computational Units
The registers in the computational units store data.
The ALU and MAC require two inputs for most operations. The AX0,
AX1, MX0 and MX1 registers store X inputs, and the AY0, AY1, MY0 and
MY1 registers store Y inputs.
The AR and AF registers store ALU results; AF can be fed back to the ALU
Y input, whereas AR can provide the X input of any computational unit.
Likewise, the MR0, MR1, MR2 and MF register store MAC results and can
be fed back for other computations. The 16-bit MR0 and MR1 registers
together with the 8-bit MR2 register can store a 40-bit multipy/accumulate
result.
The shifter can receive input from the ALU or MAC, from its own result
registers, or from a dedicated shifter input (SI) register. It can store a 32-bit
result in the SR0 and SR1 registers. The SB register stores the block
exponent for block floating-point operations. The SE register holds the
shift value for normalize and denormalize operations.
Registers in the computational units have secondary registers, shown in
Figure 12.1 as second set of registers behind the first set. Secondary
registers are useful for single-cycle context switches. The selection of these
secondary registers is controlled by a bit in the MSTAT (mode status)
register; the bit is set and cleared by these instructions:
ENA SEC_REG;
{select secondary registers}
DIS SEC_REG;
{select primary registers}
12.1.4
Bus Exchange
The PX register is an 8-bit register that allows data transfers between the
16-bit DMD bus and the 24-bit PMD bus. In a transfer between program
memory and a 16-bit register, PX provides or receives the lower eight bits.
12.1.5
Timer
The TPERIOD, TCOUNT and TSCALE hold the timer period, count and
scale factor values, respectively. These registers are memory-mapped at
locations 0x3FFD, 0x3FFC, and 0x3FFB respectively.
