ADP1974-EVALZ User Guide
UG-883
Rev. 0 | Page 7 of 12
Maximum Duty Cycle Resistor (R
DMAX
)
To customize the maximum duty cycle of the DH and DL pins
for the
ADP1974
, use Figure 14 to select R
DMAX
.
450
0
50
100
150
200
250
300
400
350
0
20
40
60
80
100
R
DM
AX
(k
Ω)
DUTY CYCLE (%)
T
A
= +25°C
13517-
014
Figure 14. R
DMAX
vs. Duty Cycle, R
FREQ
= 100 kΩ, V
COMP
= 5 V
Current-Limit Set Resistor (R
S
)
If testing the current limit in an application, use the following
equation to set the current limit:
(
)
S
PK
R
I
mV
100
mA
=
(6)
where:
I
PK
is the desired peak current limit in mA.
R
S
is the sense resistor used to set the peak current limit in Ω.
When the
ADP1974
is configured to operate in buck (charge)
mode, the internal current-limit threshold is set to 300 mV
(typical) and the negative valley current-limit threshold is set to
450 mV (typical). When the
ADP1974
is configured to operate
in boost (recycle) mode, the internal current-limit threshold is
set to 500 mV (typical). The external resistor (R
CL
) is needed to
offset the current properly to detect the peak in both buck and
boost operation. Set the R
CL
value to 20 kΩ. In operation, the
equations for setting the peak currents follow.
For buck/charge mode, the equations are
V
CL (BUCK)
= (
I
CL
) × (
R
CL
) − (
I
PK
) × (
R
S
)
(7)
V
NC (BUCK)
= (
I
CL
) × (
R
CL
) + (
I
VL(NEG)
) × (
R
S
)
(8)
For boost/recycle mode, the equation is
V
CL (BOOST)
= (
I
CL
) × (
R
CL
) + (
I
PK
) × (
R
S
)
(9)
where:
V
CL
(BUCK)
= 300 mV typical.
V
NC
(BUCK)
= 450 mV typical.
V
CL (BOOST)
= 500 mV typical.
I
PK
= peak inductor current.
I
VL(NEG)
= valley inductor current.
I
CL
= 20 µA, typical.
R
CL
= 20 kΩ.
The
ADP1974
is designed so that the peak current limit is the same
in both the buck mode and boost mode of operation. A tolerance
of 1% or better for the R
CL
and R
S
resistors is recommended.
Soft Start Capacitor (C
SS
)
The
ADP1974-EVALZ
comes with a 1 nF capacitor on the
evaluation board.
A C
SS
capacitor is not required for the
ADP1974
. When the C
SS
capacitor is not used, the internal 5 µA (typical) current source
pulls the SS pin voltage to VREG, and there is no soft start control.
Use the following equation to calculate the delay time before
switching is enabled (t
REG
):
SS
SS
REG
C
I
t
×
=
0.52
(10)
where:
I
SS
= 5 µA, typical.
C
SS
= soft start capacitor value.
During soft start, the
ADP1974
operates in asynchronous
mode, and the synchronous FET is not driven. After the soft
start period is completed (SS > 4.5 V), the
ADP1974
switches to
full synchronous mode.
VREG
4.5V
VOUT
0.52V
0V
V
SS
ENABLE
ADP1974
BEGIN
REGULATION
SYNCHRONOUS
OPERATION
t
REG
13517-
015
Figure 15. Soft Start Diagram
APPLICATION SPECIFIC
ADP1974
CONTROL
When integrated in a battery test solution, the
ADP1974
can be
controlled with external control signals from other devices in the
application. The FAULT pin allows an external device to signal
the
ADP1974
when an external fault occurs. The COMP pin
allows an external device to control the PWM output signals on
the DH and DL pins. The SYNC and SCFG pins can be used to
synchronize the
ADP1974
to an external clock signal or to
implement the
ADP1974
as a master clock. The EN and MODE
pins provide logic control to turn the
ADP1974
on or off and
to transition the system between boost/recycle mode and
buck/charge mode.
