Quick Start Guide
AD9125-EBZ
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D00000-0-1/07(A)
bypassed by enabling
PLL MANUAL
and entering a band in PLL Band Select. Divider1 and Divider0 must still be chosen appropriately
in this mode of operation.
Interrupts
This tab provides a visual indication of the state of each interrupt. Enabling the button to the left of each interrupt with enable the
interrupt. A green indicator to the right of the button will light when the interrupt is asserted. Once asserted, the interrupt can be
acknowledged by pressing the
Clear
button.
Main DAC Control
This tab controls the two main DACs in the AD9122/AD9125. The Full-Scale Current of each DAC can be set with the
I DAC Gain
and
Q
DAC Gain
controls. The
I Sleep
and
Q Sleep
controls put their respective DAC into a low-power sleep state. When the AD9122/AD9125 is
used with a modulator, the
Phase Compensation/DC
Offset controls can be used to correct any mismatches between the two DACs.
AUX DAC Control
As with the main DACs, the full-scale current of the auxiliary DACs can be set over the SPI port. Each DAC can also be powered down.
Sampling Error Detection
The Sampling Error Detection (SED) checks the data inputs. An 8-byte signature is handed to the AD9122/AD9125. The controller can
automatically generate and load the vectors using the DPG2 device. Indicators display the result of the comparison between the input
data and the expected signature.
SPI Map
The SPI Map tab provides an overview of all the settings currently written to the part. The individual register values are indicated
graphically (with red and green boxes) and numerically. The numeric results can be used in whatever system the AD9122/AD9125
connects to, to duplicate the current settings in the end system.
AD9516 Control
The evaluation board contains its own clock chip. The AD9516 has an optional on-chip PLL. The top half of the control tab helps the user
select the appropriate control values for the PLL controller. If the PLL is bypassed, the DAC Clock has the same frequency as the input to
the AD9516. Two additional clocks, Ref Clk and DCO Clk, are generated based off of the DAC Clock. The DCO Clock controlling the
data frequency can be synced with the interpolation rate on the Data Clock Control tab. If this is enabled, changing the interpolation rate
will automatically update the AD9516 to have the appropriate DCO Clock Divider Ratio.
Save and Load
The SPI controller has options to save and load all the control registers. The save takes place after the controller is run once and the load
happens before any of the read or writes to the evaluation board.
APPENDIX B - ACE SOFTWARE FEATURES
The ACE software is organized to allow the user to evaluate and control the AD9125A evaluation board. The “Initial Configuration” wizard
(Figure 6) controls the DAC and PLL setups. Block diagram views of the board (Figure 5) and chip (Figure 7) contain elements that can be
used to vary parameters like ref current and data format. These parameters can be changed using check boxes, drop down menus, and input
boxes. Some parameters do not have settings shown in the diagram. Double click on the parameter to view the available settings.
