Quick Start Guide
AD9125-EBZ
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D00000-0-1/07(A)
APPENDIX A: SPI CONTROLLER
The SPI Controller application is split into several tabs. These tabs group related functions. Several of the functions provided by the SPI
Controller are described here, as they relate to the evaluation board. For complete descriptions of each register, refer to the AD9125
datasheet. In the interest of continuous quality improvements, the images below may not exactly match your version of the software.
Running the SPI Controller
When the
Run
button is clicked, the SPI controller will run once. It will both write and read from the AD9122/AD9125 and setup the
clock chip (AD9516) on the evaluation board. The
Run Forever
control will setup both the AD9122/AD9125 and AD9516. This mode of
operation will continue to read from the chip and will update the SPI when any of the controls change. The
Force Write
and
Read Only
controls force the controller to write all the controls to the evaluation board or only read from the SPI port.
Figure 11
Data Clock Control
This section, shown in Figure 2, provides control over the Interpolation Rate and Course Modulation. Once the controller is executed,
the
Modulation Description
field will return a summary of control. If an improper selection is made, the field will return ‘Invalid.’ The
DATAFMT
field selects the number format of the incoming data, between unsigned (Binary) and signed (2’s compliment). The
QFirst
control selects which DAC receives data first from the interleaved bus. For use with the DPG2, this should always be set to
IQ Pairs
. The
Interface
Mode selects how wide the data bus will be. This setting will need to match the setting in the DPG AD9125 panel for proper
operation with the DPG2.
Figure 12
NCO Control
This tab controls the Fine Modulation within the AD9122/AD9125. The top portion of this tab helps the user easily control the frequency
shift. It will calculate the NCO Frequency using Data Frequency entered by the user. The NCO can shift the signal by at most +/- fnco/2.
An indicator also displays the frequency shift from the course modulation on the previous tab. The total shift will be the sum of the course
and fine modulations. To manually enter the Frequency Tuning Word (FTW), the Enable Advanced Control will bypass the calculations
on the top of the page.
PLL Control
The AD9122/AD9125 has an on-chip PLL. When
PLL_ENABLE
is turned on, the chip will automatically select the appropriate band
using the Divder1 and Divider0 values. This tab provides the calculation for the DAC Freq and VCO Freq based on the Reference Clock
and the value of the dividers. The VCO Frequency must be between 1 and 2 GHz for proper operation. The auto-band select can be
