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If there was no FIFO and the card could only store one sample at once, this would greatly limit the
maximum usable sample rate of the ADC. There would be a chance of missing samples if the next
one came before the previous one was read by the host.
The FIFO allows many samples to be stored locally preventing samples from being overwritten
before the host can respond to the /260+ interrupt. This feature greatly extends the
maximum sample rate of the system for multi-tasking operating systems.
The /260+ introduces two new FIFO features. The FIFO level can now be read by the
system software at any time. There is a new user programmable FIFO threshold register. The
FIFO can now be set to generate an interrupt to the host when the FIFO level reaches the
threshold. The /260+ implements the FIFO in the programmable logic inside the Field
Programmable Gate Array (FPGA).
4.4
Analog Input Modes
4.4.1
Software Controlled Sampling
The ADC can be made to take a single sample under direct software control when deterministic
sample timing is unimportant.
To complete an A/D conversion cycle under software control, first set the card into software
controlled mode and select the desired channel. Then initiate a conversion.
The ADC data word is read as one sixteen bit word.
4.4.2
Hardware Controlled Sampling
In this mode sample timing is controlled by a hardware generated clock. It has none of the variable
timing latency associated with software driven conversions and is used for acquiring continuous
time signals. The sample clock may come from one of the 82C54 counter/timers or the external
control input EXTCONVCLK / EXTTRIG if required.
If we take the most simple case where a number of samples are acquired from a single analog
channel, typically the driver software will use one of the counters to generate the sample
conversion clock. It will program the counter as a pulse generator at the required sampling interval.
The clocking frequency of each counter can be:
x
The counter/timers CLK Input from the SK1 connector
x
The Internal 10MHz clock
x
The Internal 1MHz clock
x
The Internal 100kHz clock
x
The Internal 10kHz clock
x
The Internal 1 kHz clock
x
The output of the preceding counter/timer
x
The dedicated external clock input.
The counter divide ratio loaded into the counter determines the frequency of the conversion
command signals. A single counter provides time intervals (frequencies) programmable in the
range 2.0 μSecs (500 kHz) to over 65 seconds. Longer periods can be obtained by cascading
counters.
Alternatively the conversion clock source may be from an external trigger input.
At the end of the conversion, the sample is transferred to the FIFO, if the FIFO is enabled.
Otherwise an interrupt request IRQ is transmitted to the PC.
Содержание PCI230+
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