Alphi IP-FASTDAC, Руководство владельца

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IP-FASTDAC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP. Page 4 REV 1.0
Part Number : 801-10-00-4000 Copyright ALPHI Technology Corporation, 2000
8/32Mhz register
This IP is designed to run at 32Mhz default, the register address $1A can allow 8Mhz
functionality by writing a $1 to the register. See chart below for each functions wait state.
IP-Clock DAC FUNCTION Wait States
32Mhz Stage Pre-Load 2
32Mhz Analog Output Update 3
32Mhz Direct Transfer 5
8Mhz Stage Pre-Load 2
8Mhz Analog Output Update 3
8Mhz Direct Transfer 1
2.1.3 INTSPACE
Not Used.
2.1.4 Memory space
The on board EEPROM provides 2K – 32bytes space available for the user.
2.2 ANALOG OUTPUT
The IP-FASTDAC has eight analog outputs each with its own buffer.
The outputs are +/- 10 Volts.
DAC
LTC 1821 (16bit Ultra Precise, Fast Settling Vout DAC)
+/-10Volt Bipolar Offset
Input code - Binary only
2us Settling to 0.0015% for 10volt step.
1LSB Max DNL and INL over Industrial Temp range
Low Glitch Impulse: 2nV * s
Low Noise 13nV