Alphi IP-FASTDAC Скачать руководство пользователя страница 2

IP-FASTDAC REFERENCE MANUAL

ALPHI TECHNOLOGY CORP.

Page ii 

REV 1.0

Part Number : 801-10-00-4000     Copyright ALPHI Technology Corporation, 2000

NOTICE

The information in this document has been carefully checked and is believed to be
entirely reliable. While all reasonable efforts to ensure accuracy have been taken in the
preparation of this manual, ALPHI TECHNOLOGY assumes no responsibility resulting
from omissions or errors in this manual, or from the use of information contain herein.

ALPHI TECHNOLOGY reserves the right to make any changes, without notice, to this or
any of ALPHI TECHNOLOGY’s products to improve reliability, performance, function or
design.

ALPHI TECHNOLOGY does not assume any liability arising out of the application or use
of any product or circuit described herein; nor does ALPHI TECHNOLOGY convey any
license under its patent rights or the rights of others.

ALPHI TECHNOLOGY CORPORATION

All Rights Reserved

This document shall not be duplicated, nor its contents used

for any purpose, unless express permission has been granted in advance.

Содержание IP-FASTDAC

Страница 1: ...ital to Ananlog Converter With 4 Quadrant Multiplier Industry Pack Module REFERENCE MANUAL 801 10 000 4000 Version 1 0 June 2003 ALPHI TECHNOLOGY CORPORATION 6202 S Maple Avenue 120 Tempe AZ 85283 USA...

Страница 2: ...s manual or from the use of information contain herein ALPHI TECHNOLOGY reserves the right to make any changes without notice to this or any of ALPHI TECHNOLOGY s products to improve reliability perfo...

Страница 3: ...__________ 2 2 1 1 IDSPACE ____________________________________________________________________ 2 2 1 2 IOSPACE ____________________________________________________________________ 3 2 1 3 INTSPACE __...

Страница 4: ...tional block diagram of the IP FASTDAC is presented below in Figure 1 1 The IP FASTDAC operates as a slave that is managed by the host processor on the IP bus The IP FASTDAC is supported by ALPHI Tech...

Страница 5: ...data related to the type of module revision etc The Upper space can be used to store information Only the ODD address is valid Each IP conforms to the IP Bus Specification and has 32 bytes of EEPROM...

Страница 6: ...re located in the I O space See I O memory map below for more details Offset Register Name Function 00 Ch 1 First register stage pre load of D A 1 02 Ch 2 First register stage pre load of D A 2 04 Ch...

Страница 7: ...ad 2 32Mhz Analog Output Update 3 32Mhz Direct Transfer 5 8Mhz Stage Pre Load 2 8Mhz Analog Output Update 3 8Mhz Direct Transfer 1 2 1 3 INTSPACE Not Used 2 1 4 Memory space The on board EEPROM provid...

Страница 8: ...1111 1111 0000 0000 0000 0000 Vref 32 767 32 768 Vref 1 32 768 0 volt Vref 1 32 768 Vref OUTPUT BUFFER IP FASTDAC can be configured with either a high speed high output current BUF634 or High speed l...

Страница 9: ...uration possibility Factory default for Vref is internal 10 volts A 5volt internal Vref can be accommodated upon request DAC Channel Internal Vref supply 10v External Voltage supply DAC1 W8 1 2 W8 2 3...

Страница 10: ...ignal 1 26 2 27 AGND 3 DAC 1 28 AGND 4 AGND 29 AGND 5 DAC 2 30 AGND 6 AGND 31 7 VREFX1 32 VREFX2 8 33 AGND 9 DAC 3 34 AGND 10 AGND 35 AGND 11 DAC 4 36 AGND 12 AGND 37 VREFX4 13 VREFX3 38 VREFX6 14 VRE...

Отзывы: