IP-FASTDAC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 2
REV 1.0
Part Number : 801-10-00-4000 Copyright ALPHI Technology Corporation, 2000
2. INTERNAL ORGANIZATION
The
IP-FASTDAC
card is divided into different sections. Each section and its relationship to
other sections will be discussed. The
IP-FASTDAC
sections are:
•
IP interface
•
Analog Output
2.1 IP INTERFACE
2.1.1 IDSPACE
An EEPROM memory that occupies 2 Kbytes of address space is for providing information
about the module to the user. The lower address contains data related to the type of
module, revision, etc...
The Upper space can be used to store information. Only the ODD address is valid. Each IP
conforms to the IP Bus Specification and has 32 bytes of EEPROM that can be read by the
local Host to identify the IP module Manufacturer, type, revision, etc.
Left over memory (2K-32 byte) is available to the user to store information related to the
module offset gain error for eventual software correction
ID space
address
Description
Value
$01
ASCII “I”
$49
$03
ASCII “P”
$50
$05
ASCII “A”
$41
$07
ASCII “H”
$48
$09
Manufacturer identification
$11
$0B
Module type
$17
$0D
Revision module
$0B
$0F
Reserved
$11
Driver ID,low byte
$13
Driver ID,high byte
$15
Number of bytes used
$0A
$17
CRC
$19-$3F
User space
