IP-FASTDAC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 1
REV 1.0
Part Number : 801-10-00-4000 Copyright ALPHI Technology Corporation, 2000
1. GENERAL DESCRIPTION
1.1 INTRODUCTION
The
IP-FASTDAC
is a high performance DIGITAL TO ANALOG module. The
IP-FASTDAC
digitizes 8 channels with 16 bits of resolution at a maximum conversion rate of 2
µ
S.
The primary features of the
IP-FASTDAC
are as follows:
•
Eight channels-16 bit - 2
µ
S D/A converters with on-chip 4-quadrant multiplication
resistors for ac/-10V bipolar conversion.
•
Individual buffer for each output.
•
+/-10 volt outputs.
1.2 FUNCTIONAL DESCRIPTION
A functional block diagram of the
IP-FASTDAC
is presented below in Figure 1-1.
The
IP-FASTDAC
operates as a slave that is managed by the host processor on the IP bus.
The
IP-FASTDAC
is supported by ALPHI Technology under
Windows NT
by a
Board
Support Package
which is supplied with the card. Other documentation supplied with the
card will describe this support in full detail.
Figure 1.1: Block Diagram
XLA01 - XLA06
IP
50
C
o
n
n
e
c
t
o
r
XLA01 - XLA06
CONTROL
LOGIC
IP
50
C
o
n
n
e
c
t
o
r
CONTROL SIGNALS
EEPROM
XLD00 - XLD07
LA07 - LA11
D/A
16 bits
CH # 01
Line
buffer
D/A
16 bits
CH # 02
Line
buffer
D/A
16 bits
CH # 03
Line
buffer
D/A
16 bits
CH # 04
Line
buffer
D/A
16 bits
CH # 05
Line
buffer
D/A
16 bits
CH # 06
Line
buffer
D/A
16 bits
CH # 07
Line
buffer
D/A
16 bits
CH # 08
Line
buffer
XLD00-XLD07
XLD00 - XLD15
XLD00 - XLD15
