IP-FASTDAC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 3
REV 1.0
Part Number : 801-10-00-4000 Copyright ALPHI Technology Corporation, 2000
Table 2-1 FLASH byte content
Address $01-$07 identifies “IPAH”. Also this identifies the EEprom beginning.
2.1.2 IOSPACE
2.1.2.1 LOCAL REGISTERS
The IP-FASTDAC module uses 8 - LTC1821 Ultra precise fast setting V-out D/A converters
from Linear Technology. A double buffered interface is used to transfer incoming data to
the output. The first 8 ($00 - $0E) addresses are used to pre-load data into the first stage of
each D/A converter. A write to the address $10 – DAC-OUT will transfer the data to the
outputs in a synchronous manner. The Next 8 ($20 - $2E) addresses are used to transfer
data directly to the output. The eight registers associated, one for each channel are located
in the I/O space.. See I/O memory map below for more details.
Offset
Register Name
Function
$00
Ch # 1
First register stage pre-load of D/A # 1
$02
Ch # 2
First register stage pre-load of D/A # 2
$04
Ch # 3
First register stage pre-load of D/A # 3
$06
Ch # 4
First register stage pre-load of D/A # 4
$08
Ch # 5
First register stage pre-load of D/A # 5
$0A
Ch # 6
First register stage pre-load of D/A # 6
$0C
Ch # 7
First register stage pre-load of D/A # 7
$0E
Ch # 8
First register stage pre-load of D/A # 8
$10
DAC_OUT
Analog Output update of all D/A’s
$18
DAC_RST
D/A reset
$1A
8/32Mhz
$1 = 8Mhz / $0 = 32Mhz IP-Clock
$20
Ch # 1
Direct transfer of Data to Output D/A # 1
$22
Ch # 2
Direct transfer of Data to Output D/A # 2
$24
Ch # 3
Direct transfer of Data to Output D/A # 3
$26
Ch # 4
Direct transfer of Data to Output D/A # 4
$28
Ch # 5
Direct transfer of Data to Output D/A # 5
$2A
Ch # 6
Direct transfer of Data to Output D/A # 6
$2C
Ch # 7
Direct transfer of Data to Output D/A # 7
$2E
Ch # 8
Direct transfer of Data to Output D/A # 8
Table 2.1: Registers
