ADM-PCIE-8V3 User Manual
Signal
Target FPGA Input
I/O Standard
"P" pin
"N" pin
MEM_CLK_0
IO_L13_T2L_GC_44
LVDS
G31
G32
MEM_CLK_1
IO_L11_T2L_GC_94
DIFF_HSTL_I_18
AN25
AN26
Table 11 : Memory Reference Clocks
DIFF_TERM_ADV = TRUE is required for LVDS termination
Page 10
Functional Description
ad-ug-1308_v1_9.pdf
Содержание ADM-PCIE-8V3
Страница 1: ...ADM PCIE 8V3 User Manual Document Revision 1 9 28th June 2017...
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