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61
Offset
Name
Field
Bit
Description
0xF1000208 TIMEBASE Presence_Inq [0]
Indicates
presence
of this feature (read
only)
--- [1..27]
Timebase_ID
[28..31]
IDs 0-9 are in bits 28 to 31. Refer to the following table for code.
Default timebase is
20µs.
This means that the integration time can be changed in 20 µs increments with the
shutter control.
Timebase should only be changed when the camera is in idle state and becomes active
only after setting the shutter value.
ID Timebase
ID
Timebase
0 1
µs
5
50
µs
1 2
µs
6
100
µs
2 5
µs
7
200
µs
3 10
µs
8
500
µs
4 20
µs 9
1000
µs
The ABSOLUTE VALUE CSR register, introduced in IIDC v. 1.3 is not implemented.
9.2.4
Extended shutter
The exposure time for long-term integration of up to 67 sec (SW 0.84 and FPGA FW
0.14) can be extended via the EXTENDED_SHUTTER register.
Offset
Name
Field
Bit
Description
0xF100020C
EXTD_SHUTTER
Presence_Inq
[0]
Indicates presence of
this feature (read
only)
--- [1..
5]
ExpTime
[6..31]
Exposure time in us
The longest exposure time, 3FFFFFFh, corresponds to 67.11 sec.
L
Exposure times entered via the 81Ch register are mirrored in the extended register,
but not vice versa.
9.2.5
Test images
Bits 8-14 indicate which test images are saved. Setting bits “28-31” activates or
deactivates existing test images.