Alcatel-Lucent 7950 XRS Series, Руководство по настройке

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Network Synchronization
Page 244 7950 SR OS Basic System Configuration Guide
The BITS output ports can be configured to provided either the an unfiltered recovered line clock
from a SR/ESS port or the output of the central clock of the 7750 SR. The first case would be used
if the port was connected to deliver an input reference directly to dedicated timing device in the
facility (BITS or SASE device). The second case would be used to test the quality of the clocking
used by the 7750 SR.
When QL selection mode is disabled, then the reversion setting controls when the central clock
can re-select a previously failed reference.
The Table 23 shows the selection followed for two reference in both revertive and non-revertive
modes:
Table 23: Revertive, non-Revertive Timing Reference Switching Operation
Status of
Reference A
Status of
Reference B
Active Reference
Non-revertive Case
Active Reference
Revertive Case
OK OK A A
Failed OK B B
OK OK B A
OK Failed A A
OK OK A A
Failed Failed holdover holdover
OK Failed A A
Failed Failed holdover holdover
Failed OK B B
Failed Failed holdover holdover
OK OK A or B A