Copyright © 2020
Alazar Technologies Inc.
50
ATS9353 User Manual
Fast External Clock
This setting must be used when the external clock frequency is in the range of
25 MHz to 500 MHz.
It is highly recommended that the Fast External Clock signal have a duty cycle
of 50%
±
5%. However, duty cycle specification can be substantially relaxed at
lower frequencies.
If the External Clock supplied is lower than 25 MHz, measurement quality may
be compromised. Measurement errors may include gain errors, signal
discontinuities and general signal distortion.
External Clock provides an SMA input for an external clock signal, which should
have a high slew rate. Signal levels, specified in detail in
, must be respected.
The receiver circuit for Fast External Clock acts as a high-speed analog
comparator that translates the input signal into a PECL (Positive ECL) clock
signal that features very fast rise times.
Since Fast External Clock is always ac-coupled and self-biased, there is no real
need for the user to set the external clock level.
10 MHz Reference Clock
ATS9353 allows the user to synchronize the sampling clock to an external
10 MHz reference signal. This is useful in many RF applications.
Reference clock frequency must be 10 MHz ± 0.1 MHz and should have a high
slew rate. Signal levels, specified in detail in
, must
be respected.
It should be noted that the 10 MHz reference produces a 500 MHz clock. Users
can set lower sampling frequency by specifying a decimation value (1, 2, 5, 10
or any other integer value that is divisible by 5).