Air 486PH, Руководство пользователя, Страница: 34 / 48

Chipset Setup
The BIOS Setup options described in this section are selected by
choosing the option from the Chipset Setup screen. Chipset Setup
is selected from the Setup section on the BIOS Setup main menu.
CPU to PCI Bursting
This option enables/disables PCI burst cycles for CPU-PCI write
cycles where back-to-back sequential CPU memory writes are
sent out on the PCI bus as a burst cycle. This option may help to
improve Video performance significantly. The Optimal default
setting is
Enabled . The Fail-Safe default setting is Disabled .
CPU to PCI Byte Merge
Byte merging permits the motherboard controller to merge the
data of consecutive CPU-to-PCI byte/word writes within the
same double-word address, into the posted write buffer location.
The merged collection of bytes then sent over the PCI bus as a
single double-word. Byte merging is performed in the
compatible VGA range only (0A0000-0BFFFFh) to improve
video performance. The Optimal default setting is
Enabled . The
Fail-Safe default setting is Disabled .
Cache Write Wait State
Select “Normal” for 1 waitstate cache write cycles. Select
“Fast” for 0-waitstate cache write cycle. The Optimal and Fail-
Safe default setting are
Normal .
L2 Cache Configuration
This option is reserved for Manufacturer use only. Select Non-
Interleaved for 256KB cache with 64Kx8 SRAM type installed
into the system. Normally select Interleaved .