System Details and
Performance Specifications
Clock Synthesizer 13.5 GHz User Guide
25
3.3
Internal Clock
The internal clock is generated by a fractional-N phase-locked loop (PLL)
locked to a user-selectable internal or external 10 MHz reference clock.
The PLL multiplies the reference clock up to the high-frequency (HF) output
rate. The internal reference clock is specified in Table 3.
Table 3. Parameters for N4963A 10 MHz reference
Reference
Frequency
10 MHz internal or external
10 MHz external input frequency
10 MHz ± 10 ppm
10 MHz external input amplitude range 0.5 to 2 Vpp
10 MHz reference output
500 mVpp
Interface
AC coupled, 50
Ω
nominal, female BNC
The clock synthesizer 13.5 GHz operates to 13.5 GHz.
The HF clock signal is split into three paths: an un-jittered reference path, an
optionally jittered path, and a trigger output. See the block diagram in
Figure 1.
The un-jittered reference path is available from the front-panel CH1 differential
outputs, and from the rear-panel CH3A and CH3B differential outputs. CH1 has
a programmable phase skew relative to all the other channels, programmable
output amplitude, and programmable DC offset. CH3A and CH3B share the
same programmable output amplitude.
See Table 4.
If the synthesizer includes Option 101 jitter injection, N4963A-101, the jittered
high-frequency signal will be available from the front-panel CH2 differential
outputs and the rear-panel CH4A and CH4B differential outputs. CH2 has
programmable output amplitude and programmable DC offset. CH4A and CH4B
share the same programmable output amplitude. See Table 4.
With N4963A-101, jitter can be internally generated or supplied externally.
Without N4963A-101, the un-jittered reference clock is available from CH2,
CH4A, and CH4B.
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